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11. 发明申请

US20100164567A1 INTERNAL SUPPLY VOLTAGE GENERATING CIRCUIT AND METHOD FOR GENERATING INTERNAL SUPPLY VOLTAGE 失效
标题翻译：内部电源电压生成电路及内部电源电压的生成方法
公开(公告)号：US20100164567A1
公开(公告)日：2010-07-01
申请号：US12347605
申请日：2008-12-31
申请人： Yong-Ju KIM , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Yong-Ju KIM , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03L7/00 , G11C5/14 , G05F1/10
CPC分类号： G05F1/56 , G11C5/145 , H03L7/0812 , H03L7/093
摘要： An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.
摘要翻译：内部电源电压产生电路包括：时钟比较器，被配置为将具有与参考电压电平相对应的时钟信息的第一时钟信号与具有对应于内部电源电压电平的时钟信息的第二时钟信号进行比较;控制信号发生器被配置为产生具有与所述时钟比较器的输出信号相对应的电压电平的驱动控制电压; 以及配置为响应于驱动控制电压驱动内部电源电压的端子的驱动器。

12. 发明申请

US20100064163A1 DOMAIN CROSSING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：半导体存储器装置的域交叉电路
公开(公告)号：US20100064163A1
公开(公告)日：2010-03-11
申请号：US12346675
申请日：2008-12-30
申请人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G06F1/12
CPC分类号： G11C7/1051 , G06F1/12 , G11C7/1072 , G11C7/222
摘要： A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal.
摘要翻译：半导体存储器装置的域交叉电路，域交叉电路包括在基本上相同的时钟周期产生的第一和第二计数信号，并且相对于相同位组合数据参考内部时钟信号表示预定的时钟差，以及数据处理单元，被配置为响应于与外部时钟信号同步的输入数据，基于第二计数信号提供对应于输入数据的输出数据。

13. 发明申请

US20100034043A1 SEMICONDUCTOR IC DEVICE HAVING POWER-SHARING AND METHOD OF POWER-SHARING THEREOF 失效
标题翻译：具有动力共享的半导体IC器件及其共享方法
公开(公告)号：US20100034043A1
公开(公告)日：2010-02-11
申请号：US12333194
申请日：2008-12-11
申请人： Hyung Soo Kim , Yong Ju Kim , Sung Woo Han , Hee- Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hyung Soo Kim , Yong Ju Kim , Sung Woo Han , Hee- Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C5/14 , Y10T307/352 , Y10T307/391 , Y10T307/50 , Y10T307/505 , Y10T307/549 , Y10T307/555 , Y10T307/56 , Y10T307/565 , Y10T307/571 , Y10T307/576 , Y10T307/582 , Y10T307/587 , Y10T307/593
摘要： A semiconductor IC device capable of power-sharing includes a first power line configured to be supplied with a first power, a second power line configured to be supplied with a second power, a switching block configured to connect the first power line with the second power line in response to a first control signal, and a power-sharing control block configured to generate the control signal in accordance with a plurality of operation command signals.
摘要翻译：能够进行功率共享的半导体IC器件包括被配置为被提供第一电力的第一电力线，被配置为被提供第二电力的第二电力线，被配置为将第一电力线与第二电力连接的开关块响应于第一控制信号的线路;以及功率共享控制块，被配置为根据多个操作命令信号产生控制信号。

14. 发明申请

US20090303877A1 COMMUNICATION METHOD BASED ON TRANSMISSION CONTROL PROTOCOL AND MOBILE COMMUNICATION TERMINAL TO PERFORM THE METHOD 有权
标题翻译：基于传输控制协议和移动通信终端实现方法的通信方法
公开(公告)号：US20090303877A1
公开(公告)日：2009-12-10
申请号：US12369500
申请日：2009-02-11
申请人： Hyoung Sang PARK , Hyun Soo Kim , Sung Woo Han
发明人： Hyoung Sang PARK , Hyun Soo Kim , Sung Woo Han
IPC分类号： H04L12/24
CPC分类号： H04L41/0896 , H04L41/5009
摘要： A telecommunication method based on transmission control protocol (TCP) includes setting an initial value of a congestion window according to a communication situation of a communication network to more efficiently use uncongested bandwidth of the communication network. An IP network access unit in a telecommunication network determines a congestion window value based on a predetermined reference, and transmits the determined congestion window value to the mobile telecommunication terminal. The mobile communication terminal receives the congestion window value, and performs a TCP access for data telecommunication using the initial congestion window value in a slow start algorithm of TCP in a mobile telecommunication environment. The bandwidth of telecommunication network may be more efficiently used by setting an initial value of the congestion window according to the telecommunication situation or available bandwidth.
摘要翻译：基于传输控制协议（TCP）的电信方法包括根据通信网络的通信情况来设置拥塞窗口的初始值，以更有效地使用通信网络的非占用带宽。电信网络中的IP网络接入单元基于预定参考来确定拥塞窗口值，并将所确定的拥塞窗口值发送到移动电信终端。移动通信终端接收拥塞窗口值，并且在移动电信环境中的TCP的慢启动算法中使用初始拥塞窗口值来执行数据电信的TCP接入。通过根据电信情况或可用带宽设置拥塞窗口的初始值，可以更有效地利用电信网络的带宽。

15. 发明申请

US20090257301A1 Voltage Level Comparison Circuit of Semiconductor Memory Apparatus, Voltage Adjustment Circuit Using Voltage Level Comparison Circuit, and Semiconductor Memory Apparatus Using the Same 失效
标题翻译：半导体存储器件的电压电平比较电路，使用电压电平比较电路的电压调节电路和使用其的半导体存储器件
公开(公告)号：US20090257301A1
公开(公告)日：2009-10-15
申请号：US12336423
申请日：2008-12-16
申请人： Ic Su Oh , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Ic Su Oh , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the external voltage as the output voltage.
摘要翻译：半导体存储装置的电压调整电路包括：控制电压生成部，其被配置为响应于控制信号分配用于选择性地输出多个分配电压的外部电压作为控制电压，所述多个分配电压各自具有不同的电压电平，比较单元，被配置为包括电压供应单元，其被配置为响应于所述电平的电平而控制提供给第一节点的外部电压和第二节点，如果输出电压的电平高于参考电压的电平以及检测信号生成单元，被配置为根据输出电压和参考电压的电平来降低第一和第二节点的电位电平，并输出第二节点的电位电平作为检测信号，以及电压产生单元，被配置为根据检测信号的电位来驱动外部电压并输出外部电压作为输出电压。

16. 发明申请

US20090212853A1 APPARATUS FOR SUPPLYING POWER IN SEMICONDUCTOR INTEGRATED CIRCUIT AND INPUT IMPEDANCE CONTROL METHOD OF THE SAME 审中-公开
标题翻译：用于在半导体集成电路中供电的装置及其输入阻抗控制方法
公开(公告)号：US20090212853A1
公开(公告)日：2009-08-27
申请号：US12347318
申请日：2008-12-31
申请人： Hyung-Soo Kim , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Jae Min Jang , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
发明人： Hyung-Soo Kim , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Jae Min Jang , Ji Wang Lee , Chang Kun Park , Ic Su Oh , Hae Rang Choi , Tae Jin Hwang
IPC分类号： G05F1/10 , H01L27/00
CPC分类号： H01L27/0727 , H01L29/94
摘要： An apparatus for supplying power in a semiconductor integrated circuit includes a plurality of power lines, each supplying external power to an interior of the semiconductor integrated circuit, and at least one decoupling capacitor set connected to the plurality of power lines and having a resistance value configured to be variable according to a bias voltage.
摘要翻译：一种用于在半导体集成电路中供电的装置包括多个电源线，每个电源线向半导体集成电路的内部提供外部电力，以及至少一个去耦电容器组，连接到多个电力线并具有电阻值配置根据偏置电压可变。

17. 发明授权

US08373456B2 Domain crossing circuit of a semiconductor memory apparatus 有权
标题翻译：半导体存储装置的域交叉电路
公开(公告)号：US08373456B2
公开(公告)日：2013-02-12
申请号：US12486281
申请日：2009-06-17
申请人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03L7/00
CPC分类号： H04L7/0338 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , H04L7/0045
摘要： The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.
摘要翻译：用于提高定时裕度的半导体存储装置的域交叉电路包括：采样器，其通过响应于时钟和内部输入信号产生的采样内部信号，边缘信息信号定义为输出定时采样内部信号和输出级，其允许采样内部信号与时钟同步，以响应于作为最终输出信号输出的边缘信息信号。

18. 发明授权

US08099620B2 Domain crossing circuit of a semiconductor memory apparatus 失效
标题翻译：半导体存储装置的域交叉电路
公开(公告)号：US08099620B2
公开(公告)日：2012-01-17
申请号：US12346675
申请日：2008-12-30
申请人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G06F1/00 , G06F1/04 , G06F12/00 , H03K19/00 , H03L7/00 , G11C8/00
CPC分类号： G11C7/1051 , G06F1/12 , G11C7/1072 , G11C7/222
摘要： A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal.
摘要翻译：半导体存储器装置的域交叉电路，域交叉电路包括在基本上相同的时钟周期产生的第一和第二计数信号，并且相对于相同位组合数据参考内部时钟信号表示预定的时钟差，以及数据处理单元，被配置为响应于与外部时钟信号同步的输入数据，基于第二计数信号提供对应于输入数据的输出数据。

19. 发明授权

US08035431B2 Delay locked loop and delay locking method having burst tracking scheme 有权
标题翻译：具有脉冲串跟踪方案的延迟锁定环路和延迟锁定方法
公开(公告)号：US08035431B2
公开(公告)日：2011-10-11
申请号：US12494509
申请日：2009-06-30
申请人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/093
摘要： A Delay Locked Loop (DLL) includes a replica delay unit configured to delay an output clock to generate a feedback clock; a phase detector configured to measure a phase difference between the feedback clock and an input clock; a quantization unit configured to quantize the phase difference measured by the phase detector; and a delay unit configured to delay the input clock based on a quantization result from the quantization unit to generate the output clock.
摘要翻译：延迟锁定环（DLL）包括复制延迟单元，其被配置为延迟输出时钟以产生反馈时钟; 相位检测器，被配置为测量反馈时钟和输入时钟之间的相位差; 量化单元，被配置为量化由相位检测器测量的相位差; 以及延迟单元，被配置为基于来自量化单元的量化结果来延迟输入时钟，以产生输出时钟。

20. 发明授权

US08023356B2 Voltage level comparison circuit of semiconductor memory apparatus, voltage adjustment circuit using voltage level comparison circuit, and semiconductor memory apparatus using the same 失效
标题翻译：半导体存储装置的电压电平比较电路，使用电压电平比较电路的电压调整电路和使用其的半导体存储装置
公开(公告)号：US08023356B2
公开(公告)日：2011-09-20
申请号：US12336423
申请日：2008-12-16
申请人： Ic-Su Oh , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Ic-Su Oh , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the external voltage as the output voltage.
摘要翻译：半导体存储装置的电压调整电路包括：控制电压生成部，其被配置为响应于控制信号分配用于选择性地输出多个分配电压的外部电压作为控制电压，所述多个分配电压各自具有不同的电压电平，比较单元，被配置为包括电压供应单元，其被配置为响应于所述电平的电平而控制提供给第一节点的外部电压和第二节点，如果输出电压的电平高于参考电压的电平以及检测信号生成单元，被配置为根据输出电压和参考电压的电平来降低第一和第二节点的电位电平，并输出第二节点的电位电平作为检测信号，以及电压产生单元，被配置为根据检测信号的电位来驱动外部电压并输出外部电压作为输出电压。

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