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11. 发明授权

US08312405B1 Method of placing input/output blocks on an integrated circuit device 有权
标题翻译：在集成电路设备上放置输入/输出块的方法
公开(公告)号：US08312405B1
公开(公告)日：2012-11-13
申请号：US12356349
申请日：2009-01-20
申请人： Victor Slonim , Rajat Aggarwal , Guenter Stenz , Srinivasan Dasasathyan
发明人： Victor Slonim , Rajat Aggarwal , Guenter Stenz , Srinivasan Dasasathyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of placing input/output blocks on an integrated circuit device is described. The method may comprise receiving a circuit design having a plurality of input/output blocks to be placed at input/output sites of the integrated circuit device; modifying, for each input/output block of the circuit design, an input/output standard for the input/output block to include bus information; assigning, for each input/output block of the circuit design, an input/output site for the input/output block; and generating an input/output placement for the input/output blocks of the circuit design. A computer product is also disclosed.
摘要翻译：描述了在集成电路装置上放置输入/输出块的方法。该方法可以包括接收具有多个输入/输出块以放置在集成电路器件的输入/输出位置处的电路设计; 修改对于电路设计的每个输入/输出块，输入/输出块的输入/输出标准包括总线信息; 为电路设计的每个输入/输出块分配用于输入/输出块的输入/输出站点; 以及为电路设计的输入/输出块生成输入/输出布局。还公开了一种计算机产品。

12. 发明授权

US07636876B1 Cost-based performance driven legalization technique for placement in logic designs 有权
标题翻译：基于成本的绩效驱动合法化技术用于放置在逻辑设计中
公开(公告)号：US07636876B1
公开(公告)日：2009-12-22
申请号：US11405902
申请日：2006-04-18
申请人： Sankaranarayanan Srinivasan , Srinivasan Dasasathyan
发明人： Sankaranarayanan Srinivasan , Srinivasan Dasasathyan
IPC分类号： G01R31/28 , G06F11/00 , G06F17/50
CPC分类号： G06F17/505 , G06F17/5072
摘要： A method of placing a circuit design can include selecting one or more candidate mobile nodes from a plurality of overlapped nodes of the circuit design and determining a gain region for each candidate mobile node. The method also can include assigning the candidate mobile node to a site within a gain region according to a cost function. The gain region is associated with the candidate mobile node. The method further can include iteratively selecting and assigning candidate mobile nodes according to a measure of overlap for the circuit design.
摘要翻译：放置电路设计的方法可以包括从电路设计的多个重叠节点中选择一个或多个候选移动节点，并且确定每个候选移动节点的增益区域。该方法还可以包括根据成本函数将候选移动节点分配给增益区域内的站点。增益区域与候选移动节点相关联。该方法还可以包括根据电路设计的重叠度量迭代地选择和分配候选移动节点。

13. 发明授权

US07392499B1 Placement of input/output blocks of an electronic design in an integrated circuit 有权
标题翻译：在集成电路中放置电子设计的输入/输出块
公开(公告)号：US07392499B1
公开(公告)日：2008-06-24
申请号：US11195216
申请日：2005-08-02
申请人： Guenter Stenz , Srinivasan Dasasathyan
发明人： Guenter Stenz , Srinivasan Dasasathyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5072
摘要： Approaches for placing a plurality of input/output blocks (IOBs) of an electronic design in an integrated circuit are disclosed. The electronic design includes at least one input/output bus associated with a plurality of the IOBs, and the IOBs for each input/output bus are assigned to respective sets. For each combination of pairs of the sets a respective weight factor is generated to indicate a degree of coupling between the first and second sets in the electronic design. An order of the sets is generated, and the sets are placed in an ordered series of input/output sites in the integrated circuit according to the order of the sets. A cost function is evaluated for the pairs of the sets. The generating of the order of the sets and the placing of the sets is conditionally repeated responsive to the evaluating of the cost function.
摘要翻译：公开了将电子设计的多个输入/输出块（IOB）放置在集成电路中的方法。电子设计包括与多个IOB相关联的至少一个输入/输出总线，并且用于每个输入/输出总线的IOB被分配给相应的组。对于组的成对的每个组合，生成相应的权重因子以指示电子设计中的第一和第二组之间的耦合度。生成集合的顺序，并且根据集合的顺序将集合放置在集成电路中的有序序列的输入/输出站点中。对两组的成本函数进行评估。响应于成本函数的评估，有条件地重复生成集合的顺序和集合的放置。

14. 发明授权

US07313778B1 Method system and apparatus for floorplanning programmable logic designs 有权
标题翻译：用于布局规划可编程逻辑设计的方法系统和装置
公开(公告)号：US07313778B1
公开(公告)日：2007-12-25
申请号：US10787326
申请日：2004-02-26
申请人： Guenter Stenz , Srinivasan Dasasathyan , Rajat Aggarwal , James L. Saunders
发明人： Guenter Stenz , Srinivasan Dasasathyan , Rajat Aggarwal , James L. Saunders
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5072
摘要： A method (600) of designing a programmable logic device can include the steps of identifying a cost function that penalizes floorplans of a circuit design that do not fit on the programmable logic device (605) and defining modules having components of a same type (615). A set of shapes associated with a module can be determined (610). The circuit design can be annealed (620) to determine a floorplan using the cost function and the set of shapes for the module.
摘要翻译：设计可编程逻辑器件的方法（600）可以包括以下步骤：识别损害不适合于可编程逻辑器件（605）并且限定具有相同类型的部件的模块（615）的电路设计的平面图的成本函数）。可以确定与模块相关联的一组形状（610）。电路设计可以退火（620），以使用成本函数和模块的形状集来确定平面图。

15. 发明授权

US07240315B1 Automated local clock placement for FPGA designs 有权
标题翻译： FPGA设计的自动本地时钟放置
公开(公告)号：US07240315B1
公开(公告)日：2007-07-03
申请号：US10651789
申请日：2003-08-29
申请人： Qiang Wang , Sudip K. Nag , Srinivasan Dasasathyan , James L. Saunders , Pavanish Nirula
发明人： Qiang Wang , Sudip K. Nag , Srinivasan Dasasathyan , James L. Saunders , Pavanish Nirula
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/505 , G06F17/5072 , G06F2217/08 , G06F2217/62
摘要： A method (500) of placing local clock nets in a circuit design can include identifying the local clock nets for the circuit design and selecting components corresponding to each local clock net (510,515), and assigning initial locations to each component of the local clock nets (520). The method further can include generating at least one cost function (530, 550) to evaluate (555) different placements of components of the local clock nets. The components (220, 240) of the local clock nets (205) can be annealed (535–575) using one or more of the cost functions to assign locations to each component of the local clock nets.
摘要翻译：将本地时钟网放置在电路设计中的方法（500）可以包括识别用于电路设计的本地时钟网络并且选择对应于每个本地时钟网络的组件（510,515），以及将初始位置分配给本地时钟网络的每个组件（520）。该方法还可以包括生成至少一个成本函数（530,550）以评估（555）本地时钟网络的组件的不同放置。可以使用一个或多个成本函数对本地时钟网（205）的组件（220,240）进行退火（535-575），以将位置分配给本地时钟网络的每个组件。

16. 发明授权

US07143380B1 Method for application of network flow techniques under constraints 有权
标题翻译：网络流技术在约束条件下的应用方法
公开(公告)号：US07143380B1
公开(公告)日：2006-11-28
申请号：US10215979
申请日：2002-08-08
申请人： Jason H. Anderson , Sudip K. Nag , Guenter Stenz , Srinivasan Dasasathyan
发明人： Jason H. Anderson , Sudip K. Nag , Guenter Stenz , Srinivasan Dasasathyan
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/509 , G06F2217/06
摘要： Application of network flow techniques to constrained optimization problems is disclosed. The present of constrains may lead to infeasible solutions. The infeasible solutions can be removed by an iterative process of changing the structure of the network and/or the associated parameters. Specific applications of the invention to the placement of tristate buffers and clocks in integrated circuits are disclosed.
摘要翻译：公开了网络流技术对约束优化问题的应用。约束的存在可能导致不可行的解决方案。可以通过改变网络结构和/或相关参数的迭代过程来消除不可行的解决方案。公开了本发明在集成电路中放置三态缓冲器和时钟的具体应用。

17. 发明授权

US06789244B1 Placement of clock objects under constraints 有权
标题翻译：时钟对象放置在约束下
公开(公告)号：US06789244B1
公开(公告)日：2004-09-07
申请号：US10215601
申请日：2002-08-08
申请人： Srinivasan Dasasathyan , Guenter Stenz , Sudip K. Nag
发明人： Srinivasan Dasasathyan , Guenter Stenz , Sudip K. Nag
IPC分类号： G06F1750
CPC分类号： G06F17/509 , G06F2217/06
摘要： Application of network flow techniques to constrained optimization problems is disclosed. The present of constrains may lead to infeasible solutions. The infeasible solutions can be removed by an iterative process of changing the structure of the network and/or the associated parameters. Specific applications of the invention to the placement of tristate buffers and clocks in integrated circuits are disclosed.
摘要翻译：公开了网络流技术对约束优化问题的应用。约束的存在可能导致不可行的解决方案。可以通过改变网络结构和/或相关参数的迭代过程来消除不可行的解决方案。公开了本发明在集成电路中放置三态缓冲器和时钟的具体应用。

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