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11. 发明授权

US06897136B2 Method for forming fuse in semiconductor device 失效
标题翻译：在半导体器件中形成熔丝的方法
公开(公告)号：US06897136B2
公开(公告)日：2005-05-24
申请号：US10329097
申请日：2002-12-23
申请人： Se Yeul Bae
发明人： Se Yeul Bae
IPC分类号： H01L21/82 , H01L23/525 , H01L21/44
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a fuse in a semiconductor device comprising: forming a second insulating layer on a first insulating layer; etching the second insulating layer to form a trench; depositing a first metal layer on the trench and the second insulating layer; performing a chemical-mechanical polishing (CMP) process on the first metal layer to form the first metal wiring; forming a third insulating layer on the first metal wiring and the second insulating layer; etching the third insulating layer to form a second trench; depositing a barrier layer and a second metal layer on the second trench and the third insulating layer, and performing a CMP process on the barrier layer and the third insulating layer to form the second metal wiring; depositing a buffer layer on the second metal wiring and the third insulating layer; forming a passivation layer on the buffer layer; and etching the passivation layer.
摘要翻译：一种在半导体器件中形成熔丝的方法，包括：在第一绝缘层上形成第二绝缘层; 蚀刻第二绝缘层以形成沟槽; 在所述沟槽和所述第二绝缘层上沉积第一金属层; 在所述第一金属层上进行化学机械抛光（CMP）工艺以形成所述第一金属布线; 在所述第一金属布线和所述第二绝缘层上形成第三绝缘层; 蚀刻第三绝缘层以形成第二沟槽; 在所述第二沟槽和所述第三绝缘层上沉积阻挡层和第二金属层，并且在所述阻挡层和所述第三绝缘层上进行CMP处理以形成所述第二金属布线; 在第二金属布线和第三绝缘层上沉积缓冲层; 在缓冲层上形成钝化层; 并蚀刻钝化层。

12. 发明授权

US07960839B2 Semiconductor interconnection line and method of forming the same 有权
标题翻译：半导体互连线及其形成方法
公开(公告)号：US07960839B2
公开(公告)日：2011-06-14
申请号：US11788794
申请日：2007-04-20
申请人： Se-Yeul Bae
发明人： Se-Yeul Bae
IPC分类号： H01L23/48
CPC分类号： H01L21/76808 , H01L21/76807 , H01L21/76834 , H01L21/76895
摘要： An interconnection line of a semiconductor device and a method of forming the same using a dual damascene process are disclosed. An example interconnection line of a semiconductor device includes a semiconductor substrate, a first interconnection line formed on the substrate, an insulating layer pattern formed on the substrate to expose a portion of the first interconnection line, and a metal pad layer formed on the exposed portion of the first interconnection line. The example interconnection line also includes an intermediate insulating layer formed on the entire surface of the substrate and having a via hole and a trench exposing the metal pad layer, and a second interconnection formed in the via hole and the trench and electrically connected to the first interconnection line through the metal pad layer.
摘要翻译：公开了一种半导体器件的互连线及其使用双镶嵌工艺形成该半导体器件的方法。半导体器件的示例性互连线包括半导体衬底，形成在衬底上的第一互连线，形成在衬底上以暴露第一互连线的一部分的绝缘层图案，以及形成在暴露部分上的金属衬垫层的第一条互连线。示例性互连线还包括形成在基板的整个表面上并具有暴露金属焊盘层的通孔和沟槽的中间绝缘层，以及形成在通孔和沟槽中的电连接到第一互连线通过金属焊盘层。

13. 发明申请

US20080246156A1 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US20080246156A1
公开(公告)日：2008-10-09
申请号：US12155903
申请日：2008-06-11
申请人： Se-Yeul Bae
发明人： Se-Yeul Bae
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L21/78 , H01L22/34 , H01L24/03 , H01L24/45 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05073 , H01L2224/05624 , H01L2224/05647 , H01L2224/45144 , H01L2224/4554 , H01L2224/45669 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/00014 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes: forming a first pad including a first metal and an inter-connection line including the first metal in a scribe lane region; forming a second pad including the first metal in a chip region; sequentially forming an etch-stop layer and a first insulation layer on the first pad, the inter-connection line, and the second pad; exposing the first and second pads by patterning the etch-stop layer and the first insulation layer; forming third and fourth pads including a second metal on the first and second pads; sequentially forming second and third insulation layers on the third pad, the fourth pad, and the patterned first insulation layer; and etching the first, second, and third insulation layers using the patterned photosensitive layer on the third insulation layer to expose the third and fourth pads.

14. 发明申请

US20070161232A1 METHOD FOR FORMING METAL INTERCONNECTION IN SEMICONDUTOR DAMASCENE PROCESS 审中-公开
标题翻译：在半导体大分子化学过程中形成金属互连的方法
公开(公告)号：US20070161232A1
公开(公告)日：2007-07-12
申请号：US11616273
申请日：2006-12-26
申请人： Se Yeul Bae
发明人： Se Yeul Bae
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76807 , H01L21/7685
摘要： A method for forming metal interconnections in a semiconductor damascene process, in which a selective deposition of an etch stop layer formed above a lower metal interconnection by the damascene process prevents an etch attack against the lower metal interconnection. The method includes forming a first conductive layer over a semiconductor substrate.
摘要翻译：一种用于在半导体镶嵌工艺中形成金属互连的方法，其中通过镶嵌工艺在下部金属互连上方形成的蚀刻停止层的选择性沉积防止对下部金属互连的蚀刻攻击。该方法包括在半导体衬底上形成第一导电层。

15. 发明授权

US07223686B2 Semiconductor interconnection line and method of forming the same 有权
公开(公告)号：US07223686B2
公开(公告)日：2007-05-29
申请号：US11026717
申请日：2004-12-30
申请人： Se-Yeul Bae
发明人： Se-Yeul Bae
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76807 , H01L21/76834 , H01L21/76895
摘要： An interconnection line of a semiconductor device and a method of forming the same using a dual damascene process are disclosed. An example interconnection line of a semiconductor device includes a semiconductor substrate, a first interconnection line formed on the substrate, an insulating layer pattern formed on the substrate to expose a portion of the first interconnection line, and a metal pad layer formed on the exposed portion of the first interconnection line. The example interconnection line also includes an intermediate insulating layer formed on the entire surface of the substrate and having a via hole and a trench exposing the metal pad layer, and a second interconnection formed in the via hole and the trench and electrically connected to the first interconnection line through the metal pad layer.

16. 发明申请

US20060138589A1 Semiconductor device with a fuse part and method of manufacturing the same 失效
标题翻译：具有保险丝部件的半导体器件及其制造方法
公开(公告)号：US20060138589A1
公开(公告)日：2006-06-29
申请号：US11318637
申请日：2005-12-28
申请人： Se-Yeul Bae
发明人： Se-Yeul Bae
IPC分类号： H01L29/00 , H01L27/10
CPC分类号： H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device with a fuse part and a method of forming the same. The method includes forming a selective metal layer on a via hole which is connected to a metal line in a semiconductor device, forming a fuse metal layer on the selective metal layer, and forming a fuse metal layer pattern by using a photosensitive layer pattern which is formed on the fuse metal layer.
摘要翻译：本发明提供一种具有熔丝部分的半导体器件及其形成方法。该方法包括在通孔上形成选择性金属层，所述通孔与半导体器件中的金属线连接，在选择性金属层上形成熔丝金属层，并通过使用感光层图案形成熔丝金属层图案，该感光层图案是形成在熔丝金属层上。

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