专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08629513B2 HV interconnection solution using floating conductors 有权
标题翻译：使用浮动导体的HV互连解决方案
公开(公告)号：US08629513B2
公开(公告)日：2014-01-14
申请号：US13007220
申请日：2011-01-14
申请人： Ru-Yi Su , Fu-Chih Yang , Chun-Lin Tsai , Ker Hsiao Huo , Chih-Chang Cheng , Ruey-Hsin Liu
发明人： Ru-Yi Su , Fu-Chih Yang , Chun-Lin Tsai , Ker Hsiao Huo , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L27/088 , H01L29/0692 , H01L29/0696 , H01L29/404 , H01L29/42368 , H01L29/4238 , H01L29/7816 , H01L29/861
摘要： A device includes a first and a second heavily doped region in a semiconductor substrate. An insulation region has at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions. A gate dielectric is formed over the semiconductor substrate and having a portion over a portion of the insulation region. A gate is formed over the gate dielectric. A floating conductor is over and vertically overlapping the insulation region. A metal line includes a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region.
摘要翻译：一种器件包括半导体衬底中的第一和第二重掺杂区域。绝缘区域在半导体衬底中具有至少一部分，其中绝缘区域与第一和第二重掺杂区域相邻。栅极电介质形成在半导体衬底之上并且具有在绝缘区域的一部分上的部分。栅极形成在栅极电介质上。浮动导体在绝缘区域上方和上方重叠。金属线包括在浮动导体上方并垂直重叠的部分，其中金属线与第二重掺杂区耦合并承载第二重掺杂区的电压。

12. 发明授权

US08587073B2 High voltage resistor 有权
公开(公告)号：US08587073B2
公开(公告)日：2013-11-19
申请号：US12905840
申请日：2010-10-15
申请人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen (Albert) Yao , Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai
发明人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen (Albert) Yao , Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L23/62
CPC分类号： H01L29/66166 , H01L23/5228 , H01L27/0288 , H01L27/0802 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities.

13. 发明申请

US20120319240A1 High Voltage Resistor With Pin Diode Isolation 有权
标题翻译：高压电阻与引脚二极管隔离
公开(公告)号：US20120319240A1
公开(公告)日：2012-12-20
申请号：US13160030
申请日：2011-06-14
申请人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
发明人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号： H01L29/8605 , H01L21/20
CPC分类号： H01L29/0649 , H01L21/26513 , H01L21/74 , H01L21/761 , H01L21/76202 , H01L23/528 , H01L27/0676 , H01L27/0802 , H01L28/20 , H01L29/0692 , H01L29/456 , H01L29/6609 , H01L29/8605 , H01L29/868
摘要： Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.
摘要翻译：提供一种高压半导体器件，其包括形成在衬底中的PIN二极管结构。 PIN二极管包括位于第一掺杂阱和第二掺杂阱之间的本征区。第一和第二掺杂阱具有与内部区域相反的掺杂极性和更大的掺杂浓度水平。半导体器件包括形成在第一掺杂阱的一部分上的绝缘结构。半导体器件包括形成在绝缘结构上的细长电阻器件。电阻器件分别设置在电阻器件的相对端处的第一和第二部分。半导体器件包括形成在电阻器件上的互连结构。互连结构包括：电耦合到第一掺杂阱的第一接触和电耦合到位于第一和第二部分之间的电阻器的第三部分的第二接触。

14. 发明申请

US20120091529A1 HIGH VOLTAGE RESISTOR 有权
标题翻译：高压电阻
公开(公告)号：US20120091529A1
公开(公告)日：2012-04-19
申请号：US12905840
申请日：2010-10-15
申请人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen (Albert) Yao , Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai
发明人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen (Albert) Yao , Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L29/66166 , H01L23/5228 , H01L27/0288 , H01L27/0802 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities.
摘要翻译：提供一种半导体器件。半导体器件包括电阻器和电压保护器件。电阻器具有螺旋形状。电阻器具有第一部分和第二部分。电压保护装置包括电耦合到电阻器的第一部分的第一掺杂区域。电压保护装置包括电耦合到电阻器的第二部分的第二掺杂区域。第一和第二掺杂区具有相反的掺杂极性。

15. 发明申请

US20140021560A1 HIGH VOLTAGE DEVICE WITH A PARALLEL RESISTOR 有权
标题翻译：具有并联电阻的高电压装置
公开(公告)号：US20140021560A1
公开(公告)日：2014-01-23
申请号：US13551262
申请日：2012-07-17
申请人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Ker Hsiao Huo , Jen-Hao Yeh , Chun-Wei Hsu
发明人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Ker Hsiao Huo , Jen-Hao Yeh , Chun-Wei Hsu
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0629
摘要： Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a transistor having a gate, a source, and a drain. The source and the drain are formed in a doped substrate and are separated by a drift region of the substrate. The gate is formed over the drift region and between the source and the drain. The transistor is configured to handle high voltage conditions that are at least a few hundred volts. The high voltage semiconductor device includes a dielectric structure formed between the source and the drain of the transistor. The dielectric structure protrudes into and out of the substrate. Different parts of the dielectric structure have uneven thicknesses. The high voltage semiconductor device includes a resistor formed over the dielectric structure. The resistor has a plurality of winding segments that are substantially evenly spaced apart.
摘要翻译：提供高压半导体器件。高电压半导体器件包括具有栅极，源极和漏极的晶体管。源极和漏极形成在掺杂衬底中并且由衬底的漂移区域分离。栅极形成在漂移区域上以及源极和漏极之间。晶体管被配置为处理至少几百伏特的高电压条件。高电压半导体器件包括在晶体管的源极和漏极之间形成的电介质结构。电介质结构突出进出基板。电介质结构的不同部分具有不均匀的厚度。高电压半导体器件包括在电介质结构上形成的电阻器。电阻器具有大致均匀间隔开的多个绕组段。

16. 发明授权

US08629026B2 Source tip optimization for high voltage transistor devices 有权
标题翻译：高压晶体管器件的源尖优化
公开(公告)号：US08629026B2
公开(公告)日：2014-01-14
申请号：US12944959
申请日：2010-11-12
申请人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
发明人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号： H01L21/22 , H01L21/331 , H01L21/336 , H01L21/38 , H01L21/425
CPC分类号： H01L29/7816 , H01L21/2253 , H01L21/26513 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/105 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/66795 , H01L29/7835
摘要： The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.
摘要翻译：本公开提供了一种用于制造高压半导体器件的方法。该方法包括在衬底中指定第一，第二和第三区域。第一和第二区域分别是将形成半导体器件的源极和漏极的区域。第三区域分隔第一和第二区域。该方法还包括至少部分地在第三区域上形成开槽的注入掩模层。该方法还包括将掺杂剂注入到第一，第二和第三区域中。开槽植入物掩模层在植入期间保护其下方的第三区域的部分。该方法还包括以使得掺杂剂在第三区域中扩散的方式退火衬底。

17. 发明授权

US08575694B2 Insulated gate bipolar transistor structure having low substrate leakage 有权
公开(公告)号：US08575694B2
公开(公告)日：2013-11-05
申请号：US13372037
申请日：2012-02-13
申请人： Ker Hsiao Huo , Chih-Chang Cheng , Ru-Yi Su , Jen-Hao Yeh , Fu-Chih Yang , Chun Lin Tsai
发明人： Ker Hsiao Huo , Chih-Chang Cheng , Ru-Yi Su , Jen-Hao Yeh , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L29/66 , H01L29/786 , H01L29/02 , H01L23/58 , H01L21/70 , H01L21/336 , H01L21/8238
CPC分类号： H01L29/7394 , H01L21/26533 , H01L21/76243 , H01L21/76283 , H01L29/063 , H01L29/0649 , H01L29/0653 , H01L29/0865 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/42368 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66325 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7824 , H01L2924/0002 , H01L2924/00
摘要： A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

18. 发明申请

US20130207187A1 INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE HAVING LOW SUBSTRATE LEAKAGE 有权
标题翻译：具有低基板泄漏的绝缘栅双极晶体管结构
公开(公告)号：US20130207187A1
公开(公告)日：2013-08-15
申请号：US13372037
申请日：2012-02-13
申请人： Ker Hsiao HUO , Chih-Chang CHENG , Ru-Yi SU , Jen-Hao YEH , Fu-Chih YANG , Chun Lin TSAI
发明人： Ker Hsiao HUO , Chih-Chang CHENG , Ru-Yi SU , Jen-Hao YEH , Fu-Chih YANG , Chun Lin TSAI
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7394 , H01L21/26533 , H01L21/76243 , H01L21/76283 , H01L29/063 , H01L29/0649 , H01L29/0653 , H01L29/0865 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/42368 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66325 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7824 , H01L2924/0002 , H01L2924/00
摘要： A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.
摘要翻译：在本公开中提供了高电压金属氧化物半导体横向扩散器件（HV LDMOS），特别是绝缘栅双极结型晶体管（IGBT）及其制造方法。该器件包括半导体衬底，形成在衬底上的栅极结构，在栅极结构的任一侧上的衬底中形成的源极和漏极，在衬底中形成的第一掺杂阱和形成在第一衬底中的第二掺杂阱好。栅极，源极，第二掺杂阱，第一阱的一部分和漏极结构的一部分被硅衬底中的深沟槽隔离特征和注入的氧层包围。

19. 发明申请

US20120280361A1 HIGH VOLTAGE RESISTOR WITH BIASED-WELL 有权
标题翻译：高压电阻器
公开(公告)号：US20120280361A1
公开(公告)日：2012-11-08
申请号：US13100714
申请日：2011-05-04
申请人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
发明人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号： H01L29/8605 , H01L21/02
CPC分类号： H01L28/20 , H01L27/0207 , H01L27/0802
摘要： Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L.
摘要翻译：提供高压半导体器件。半导体器件包括位于衬底中的相对掺杂的掺杂阱。半导体器件包括位于掺杂阱上的电介质结构。邻近电介质结构的掺杂阱的一部分具有比掺杂阱的剩余部分更高的掺杂浓度。半导体器件包括位于电介质结构上的细长多晶硅结构。细长多晶硅结构具有长度L.与电介质结构相邻的掺杂阱的部分电耦合到细长多晶硅结构的段，其远离细长多晶硅结构的中点远离所测量的预定距离细长多晶硅结构。预定距离在从大约0 * L到大约0.1 * L的范围内。

20. 发明申请

US20120181629A1 HV Interconnection Solution Using Floating Conductors 有权
标题翻译：使用浮动导体的HV互连解决方案
公开(公告)号：US20120181629A1
公开(公告)日：2012-07-19
申请号：US13007220
申请日：2011-01-14
申请人： Ru-Yi Su , Fu-Chih Yang , Chun-Lin Tsai , Ker Hsiao Huo , Chih-Chang Cheng , Ruey-Hsin Liu
发明人： Ru-Yi Su , Fu-Chih Yang , Chun-Lin Tsai , Ker Hsiao Huo , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L27/088 , H01L29/0692 , H01L29/0696 , H01L29/404 , H01L29/42368 , H01L29/4238 , H01L29/7816 , H01L29/861
摘要： A device includes a first and a second heavily doped region in a semiconductor substrate. An insulation region has at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions. A gate dielectric is formed over the semiconductor substrate and having a portion over a portion of the insulation region. A gate is formed over the gate dielectric. A floating conductor is over and vertically overlapping the insulation region. A metal line includes a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region.
摘要翻译：一种器件包括半导体衬底中的第一和第二重掺杂区域。绝缘区域在半导体衬底中具有至少一部分，其中绝缘区域与第一和第二重掺杂区域相邻。栅极电介质形成在半导体衬底之上并且具有在绝缘区域的一部分上的部分。栅极形成在栅极电介质上。浮动导体在绝缘区域上方和上方重叠。金属线包括在浮动导体上方并垂直重叠的部分，其中金属线与第二重掺杂区耦合并承载第二重掺杂区的电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式