专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US09263599B2 Semiconductor system and method for manufacturing same 有权
标题翻译：半导体系统及其制造方法
公开(公告)号：US09263599B2
公开(公告)日：2016-02-16
申请号：US13382986
申请日：2010-06-09
申请人： Ning Qu , Alfred Goerlach
发明人： Ning Qu , Alfred Goerlach
IPC分类号： H01L21/20 , H01L29/06 , H01L29/872 , H01L29/66
CPC分类号： H01L29/8725 , H01L29/0623 , H01L29/0626 , H01L29/66143
摘要： A semiconductor system having a trench MOS barrier Schottky diode is described, including an n-type epitaxial layer, in which at least two etched trenches are located in a two-dimensional manner of presentation on an n+-type substrate which acts as the cathode zone. An electrically floating, p-type layer, which acts as the anode zone of the p-n type diode, is located in the n-type epitaxial layer, at least in a location below the trench bottom. An oxide layer is located between a metal layer and the surface of the trenches. The n-type epitaxial layer may include two n-type layers of different doping concentrations.
摘要翻译：描述了具有沟槽MOS势垒肖特基二极管的半导体系统，其包括n型外延层，其中至少两个蚀刻沟槽以二维呈现方式位于作为阴极区的n +型衬底上。充当p-n型二极管的阳极区的电浮动p型层至少位于沟槽底部下方的位置，位于n型外延层中。氧化物层位于金属层和沟槽表面之间。 n型外延层可以包括不同掺杂浓度的两个n型层。

12. 发明授权

US08497563B2 Semiconductor device and method for its manufacture 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08497563B2
公开(公告)日：2013-07-30
申请号：US12733753
申请日：2008-09-15
申请人： Ning Qu , Alfred Goerlach
发明人： Ning Qu , Alfred Goerlach
IPC分类号： H01L29/66
CPC分类号： H01L29/0634 , H01L29/0619 , H01L29/0649 , H01L29/872 , H01L29/8725
摘要： A semiconductor system having a trench MOS barrier Schottky diode, having an integrated substrate PN diode as a clamping element (TMBS-ub-PN), suitable in particular as a Zener diode having a breakdown voltage of approximately 20V for use in a vehicle generator system, the TMBS-sub-PN being made up of a combination of Schottky diode, MOS structure, and substrate PN diode, and the breakdown voltage of substrate PN diode BV_pn being lower than the breakdown voltage of Schottky diode BV_schottky and the breakdown voltage of MOS structure BV_mos.
摘要翻译：具有沟槽MOS势垒肖特基二极管的半导体系统，其具有作为钳位元件（TMBS-ub-PN）的集成衬底PN二极管，特别适用于具有大约20V的击穿电压的齐纳二极管，用于车辆发电机系统 TMBS-sub-PN由肖特基二极管，MOS结构和衬底PN二极管的组合构成，并且衬底PN二极管BV_pn的击穿电压低于肖特基二极管BV_肖特基的击穿电压和MOS的击穿电压结构BV_mos。

13. 发明申请

US20130161779A1 SUPER TRENCH SCHOTTKY BARRIER SCHOTTKY DIODE 有权
标题翻译：超级TRENCH SCHOTTKY BARRIER肖特基二极管
公开(公告)号：US20130161779A1
公开(公告)日：2013-06-27
申请号：US13691038
申请日：2012-11-30
申请人： Ning Qu , Alfred Goerlach
发明人： Ning Qu , Alfred Goerlach
IPC分类号： H01L29/872
CPC分类号： H01L29/8725 , H01L29/47
摘要： A Schottky diode includes an n+-substrate, an n-epilayer, trenches introduced into the n-epilayer, floating Schottky contacts being located on their side walls and on the entire trench bottom, mesa regions between the adjacent trenches, a metal layer on its back face, this metal layer being used as a cathode electrode, and an anode electrode on the front face of the Schottky diode having two metal layers, the first metal layer of which forms a Schottky contact and the second metal layer of which is situated below the first metal layer and also forms a Schottky contact. Preferably, these two Schottky contacts have different barrier heights.
摘要翻译：肖特基二极管包括n +衬底，n外延层，引入n外延层的沟槽，浮动肖特基触点位于其侧壁和整个沟槽底部，相邻沟槽之间的台面区域，其上的金属层背面，该金属层用作阴极电极，并且在肖特基二极管的正面上的阳极电极具有两个金属层，第一金属层形成肖特基接触，第二金属层位于下面第一金属层并形成肖特基接触。优选地，这两个肖特基接触具有不同的屏障高度。

14. 发明申请

US20120198514A1 Methods and Apparatuses for User-Verifiable Trusted Path in the Presence of Malware 有权
标题翻译：恶意软件存在的用户可验证信任路径的方法和设备
公开(公告)号：US20120198514A1
公开(公告)日：2012-08-02
申请号：US13389212
申请日：2010-06-29
申请人： Jonathan M. McCune , Adrian M. Perrig , Anupam Datta , Virgil D. Gligor , Ning Qu
发明人： Jonathan M. McCune , Adrian M. Perrig , Anupam Datta , Virgil D. Gligor , Ning Qu
IPC分类号： G06F21/00
CPC分类号： G06F21/57 , G06F21/85
摘要： An apparatus and method for establishing a trusted path between a user interface and a trusted executable, wherein the trusted path includes a hypervisor and a driver shim. The method includes measuring an identity of the hypervisor; comparing the measurement of the identity of the hypervisor with a policy for the hypervisor; measuring an identity of the driver shim; comparing the measurement of the identity of the driver shim with a policy for the driver shim; measuring an identity of the user interface; comparing the measurement of the identity of the user interface with a policy for the user interface; and providing a human-perceptible indication of whether the identity of the hypervisor, the identity of the driver shim, and the identity of the user interface correspond with the policy for the hypervisor, the policy for the driver shim, and the policy for the user interface, respectively.
摘要翻译：一种用于在用户界面和可信赖可执行程序之间建立可信路径的装置和方法，其中所述可信路径包括管理程序和驱动器垫片。该方法包括测量管理程序的身份; 将管理程序的身份的测量与管理程序的策略进行比较; 测量驾驶员垫片的身份; 将驾驶员垫片的身份的测量与驾驶员垫片的策略进行比较; 测量用户界面的身份; 将用户界面的身份的测量与用户界面的策略进行比较; 以及提供关于虚拟机管理程序的身份，驱动程序垫片的身份以及用户界面的身份是否符合管理程序的策略，驱动程序垫片的策略以及用户策略的人为可察觉的指示界面。

15. 发明申请

US20110212602A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110212602A1
公开(公告)日：2011-09-01
申请号：US13104168
申请日：2011-05-10
申请人： Alfred GOERLACH , Ning Qu
发明人： Alfred GOERLACH , Ning Qu
IPC分类号： H01L21/20 , H01L21/22 , H01L21/223 , H01L21/265
CPC分类号： H01L29/8725 , H01L29/66143 , H01L29/861 , H01L29/872
摘要： A semiconductor device includes a trench MOS barrier Schottky diode having an integrated PN diode and a method is for manufacturing same.
摘要翻译：半导体器件包括具有集成PN二极管的沟槽MOS势垒肖特基二极管及其制造方法。

16. 发明申请

US20100301387A1 SEMICONDUCTOR DEVICE AND METHOD FOR ITS PRODUCTION 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100301387A1
公开(公告)日：2010-12-02
申请号：US12733775
申请日：2008-09-17
申请人： Ning Qu , Alfred Goerlach
发明人： Ning Qu , Alfred Goerlach
IPC分类号： H01L29/866 , H01L29/739
CPC分类号： H01L29/868 , H01L29/0611 , H01L29/0623 , H01L29/161 , H01L29/861 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor system is described, which is made up of a highly n-doped silicon substrate and a first n-silicon epitaxial layer, which is directly contiguous to the highly n-doped silicon substrate, and having a p-doped SiGe layer, which is contiguous to a second n-doped silicon epitaxial layer and forms a heterojunction diode, which is situated above the first n-doped silicon epitaxial layer and in which the pn-junction is situated within the p-doped SiGe layer. The first n-silicon epitaxial layer has a higher doping concentration than the second n-silicon epitaxial layer. Situated between the two n-doped epitaxial layers is at least one p-doped emitter trough, which forms a buried emitter, a pn-junction both to the first n-doped silicon epitaxial layer and also to the second n-doped silicon epitaxial layer being formed, and the at least one emitter trough being completely enclosed by the two epitaxial layers.
摘要翻译：描述了半导体系统，其由高度n掺杂的硅衬底和与第一n型硅衬底直接相邻并具有p掺杂的SiGe层的第一n型硅外延层组成，其中与第二n掺杂硅外延层邻接并形成异质结二极管，其位于第一n掺杂硅外延层之上，并且其中pn结位于p掺杂SiGe层内。第一n硅外延层具有比第二n硅外延层更高的掺杂浓度。位于两个n掺杂外延层之间的是至少一个p掺杂的发射极沟槽，其形成掩埋发射极，pn结与第一n掺杂硅外延层以及第二n掺杂硅外延层并且所述至少一个发射极槽被两个外延层完全包围。

17. 发明申请

US20080128850A1 Semiconductor Device And Method For Manufacturing Same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20080128850A1
公开(公告)日：2008-06-05
申请号：US11667440
申请日：2005-09-13
申请人： Alfred Goerlach , Ning Qu
发明人： Alfred Goerlach , Ning Qu
IPC分类号： H01L29/872 , H01L21/329
CPC分类号： H01L29/8725 , H01L29/66143 , H01L29/861 , H01L29/872
摘要： A semiconductor device (20) comprising a trench MOS barrier Schottky diode having an integrated PN diode and a method for manufacturing same are described.
摘要翻译：描述了包括具有集成PN二极管的沟槽MOS势垒肖特基二极管及其制造方法的半导体器件（20）。

18. 发明授权

US09263597B2 Semiconductor arrangement having a Schottky diode 有权
标题翻译：具有肖特基二极管的半导体装置
公开(公告)号：US09263597B2
公开(公告)日：2016-02-16
申请号：US13882412
申请日：2011-09-09
申请人： Ning Qu , Alfred Goerlach
发明人： Ning Qu , Alfred Goerlach
IPC分类号： H01L29/872 , H01L29/40 , H01L29/417
CPC分类号： H01L29/872 , H01L29/404 , H01L29/417
摘要： A semiconductor assemblage of a super-trench Schottky barrier diode (STSBD) made up of an n+ substrate, an n-epilayer, trenches etched into the n-epilayer that have a width and a distance from the n+ substrate, mesa regions between the adjacent trenches having a width, a metal layer on the front side of the chip that is a Schottky contact and serves as an anode electrode, and a metal layer on the back side of the chip that is an ohmic contact and serves as a cathode electrode, wherein multiple Schottky contacts having a width or distance and a distance between the Schottky contacts, and between the Schottky contact as anode electrode and the first Schottky contact, are located on the trench wall.
摘要翻译：由n +衬底，n-外延层，蚀刻到n-外延层中的与n +衬底具有宽度和距离的沟槽组成的超沟槽肖特基势垒二极管（STSBD）的半导体组件，相邻的n +衬底之间的台面区域具有宽度的沟槽，作为肖特基接触的芯片的前侧上的金属层，用作阳极电极，以及作为欧姆接触并用作阴极电极的芯片背面的金属层，其中具有宽度或距离以及肖特基接触之间以及作为阳极电极的肖特基接触和第一肖特基接触之间的多个肖特基接触位于沟槽壁上。

19. 发明授权

US09082628B2 Trench schottky diode 有权
标题翻译：沟槽肖特基二极管
公开(公告)号：US09082628B2
公开(公告)日：2015-07-14
申请号：US13984604
申请日：2011-12-14
申请人： Ning Qu , Alfred Goerlach
发明人： Ning Qu , Alfred Goerlach
IPC分类号： H01L29/47 , H01L29/06 , H01L29/36 , H01L29/872
CPC分类号： H01L29/0615 , H01L29/36 , H01L29/872 , H01L29/8725
摘要： A trench Schottky diode is described, which has a highly doped substrate of a first conductivity type and an epitaxial layer of the same conductivity type that is applied to the substrate. At least two trenches are introduced into the epitaxial layer. The epitaxial layer is a stepped epitaxial layer that has two partial layers of different doping concentrations.
摘要翻译：描述了一种沟槽肖特基二极管，其具有第一导电类型的高掺杂衬底和施加到衬底的相同导电类型的外延层。至少两个沟槽被引入到外延层中。外延层是具有不同掺杂浓度的两个部分层的阶梯式外延层。

20. 发明申请

US20150091125A1 SEMICONDUCTOR ARRAY HAVING TEMPERATURE-COMPENSATED BREAKDOWN VOLTAGE 有权
标题翻译：半导体阵列具有温度补偿的断电电压
公开(公告)号：US20150091125A1
公开(公告)日：2015-04-02
申请号：US14504965
申请日：2014-10-02
申请人： Alfred GOERLACH , Ning Qu
发明人： Alfred GOERLACH , Ning Qu
IPC分类号： H01L27/06 , H01L29/06 , H01L29/732 , H01L29/16 , H01L29/872 , H01L29/73
CPC分类号： H01L27/0664 , H01L27/0766 , H01L29/0615 , H01L29/0619 , H01L29/16 , H01L29/36 , H01L29/66143 , H01L29/7302 , H01L29/732 , H01L29/861 , H01L29/872 , H01L29/8725
摘要： A semiconductor array is described whose breakdown voltage has only a very low temperature coefficient or none at all and therefore there is little or no temperature-dependent voltage rise. The voltage limitation is achieved by a punch-through effect.
摘要翻译：描述了其击穿电压仅具有非常低的温度系数或根本不存在的半导体阵列，因此几乎没有或没有温度依赖的电压上升。电压限制通过穿通效果实现。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式