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11. 发明授权

US5582640A Semiconductor device and its fabricating method 失效
公开(公告)号：US5582640A
公开(公告)日：1996-12-10
申请号：US56443
申请日：1993-04-30
申请人： Takako Okada , Shigeru Kambayashi , Moto Yabuki , Shinji Onga , Yoshitaka Tsunashima , Yuuichi Mikata , Haruo Okano
发明人： Takako Okada , Shigeru Kambayashi , Moto Yabuki , Shinji Onga , Yoshitaka Tsunashima , Yuuichi Mikata , Haruo Okano
IPC分类号： H01L21/02 , H01L21/20 , H01L21/28 , H01L21/329 , H01L21/334 , H01L21/336 , H01L21/822 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/12 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L28/82 , H01L21/2022 , H01L21/28035 , H01L29/6609 , H01L29/66181 , H01L29/66613 , H01L29/66628 , H01L29/66651 , H01L29/66757 , H01L29/66765 , H01L29/78675 , H01L29/78678 , H01L29/49 , H01L29/78654
摘要： A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal. In another embodiment of the present invention, an amorphous semiconductor thin film is formed on a substrate or an insulating film such that an average inter-atomic distance distribution of main constituent element of the film substantially coincides with an average inter-atomic distance distribution of the element in a single crystal, and crystallization energy is applied to the amorphous semiconductor thin film to cause solid phase growth to thereby form a single crystalline semiconductor thin film.

12. 发明授权

US08309958B2 Semiconductor memory device and method of manufacturing same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08309958B2
公开(公告)日：2012-11-13
申请号：US12872284
申请日：2010-08-31
申请人： Jun Hirota , Yoko Iwakaji , Moto Yabuki
发明人： Jun Hirota , Yoko Iwakaji , Moto Yabuki
IPC分类号： H01L29/06 , H01L29/12 , H01L45/00
CPC分类号： H01L27/1021 , H01L27/101
摘要： According to one embodiment, a semiconductor memory device includes a word line interconnection layer, a bit line interconnection layer and a pillar. The word line interconnection layer includes a plurality of word lines which extend in a first direction. The bit line interconnection layer includes a plurality of bit lines which extend in a second direction crossing over the first direction. The pillar is arranged between each of the word lines and each of the bit lines. The pillar includes a silicon diode and a variable resistance film, and the silicon diode includes a p-type portion and an n-type portion. The word line interconnection layer and the bit line interconnection layer are alternately stacked, and a compressive force is applied to the silicon diode in a direction in which the p-type portion and the n-type portion become closer to each other.
摘要翻译：根据一个实施例，半导体存储器件包括字线互连层，位线互连层和柱。字线互连层包括沿第一方向延伸的多个字线。位线互连层包括沿与第一方向交叉的第二方向延伸的多个位线。支柱布置在每个字线和每个位线之间。支柱包括硅二极管和可变电阻膜，并且硅二极管包括p型部分和n型部分。字线互连层和位线互连层交替堆叠，并且在p型部分和n型部分变得更接近的方向上对硅二极管施加压缩力。

13. 发明申请

US20120091414A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120091414A1
公开(公告)日：2012-04-19
申请号：US13052143
申请日：2011-03-21
申请人： Yoko IWAKAJI , Jun Hirota , Moto Yabuki , Wakana Kai , Hirokazu Ishida , Ichiro Mizushima
发明人： Yoko IWAKAJI , Jun Hirota , Moto Yabuki , Wakana Kai , Hirokazu Ishida , Ichiro Mizushima
IPC分类号： H01L47/00 , H01L21/20 , H01L29/04
CPC分类号： H01L29/045 , H01L21/02425 , H01L21/0245 , H01L21/02502 , H01L21/02516 , H01L21/02532 , H01L21/02609 , H01L21/02667 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L29/685 , H01L29/868 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/16 , H01L45/1675
摘要： According to one embodiment, a semiconductor device includes a plurality of silicon films. The plurality of silicon films are disposed on one plane and are made of polysilicon containing an impurity. A crystal orientation of each of the silicon films is a (311) orientation.
摘要翻译：根据一个实施例，半导体器件包括多个硅膜。多个硅膜设置在一个平面上，由含有杂质的多晶硅制成。每个硅膜的晶体取向为（311）取向。

14. 发明申请

US20090212352A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20090212352A1
公开(公告)日：2009-08-27
申请号：US12391953
申请日：2009-02-24
申请人： Kenji AOYAMA , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
发明人： Kenji AOYAMA , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
IPC分类号： H01L29/792 , H01L21/28 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/764 , H01L29/66825
摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.
摘要翻译：半导体存储器件具有半导体衬底，在半导体衬底上以预定间隔形成的多个字线，每个字线具有栅极绝缘膜，电荷存储层，第一绝缘膜和控制栅电极，它们被堆叠并且包括位于栅极绝缘膜的高度之上的金属氧化物层，覆盖字线的一侧的第二绝缘膜和字线之间的半导体衬底的表面，并且具有15nm的膜厚度或并且形成在彼此相邻的字线之间的第三绝缘膜，使得低于金属氧化物层的电平的区域具有空腔。

15. 发明申请

US20050127513A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050127513A1
公开(公告)日：2005-06-16
申请号：US11042176
申请日：2005-01-26
申请人： Moto Yabuki
发明人： Moto Yabuki
IPC分类号： H01L27/105 , H01L21/02 , H01L21/20 , H01L21/768 , H01L21/8246 , H01L23/48 , H01L27/115
CPC分类号： H01L27/11502 , H01L21/76838 , H01L27/11507 , H01L28/40 , H01L28/82
摘要： Disclosed is a semiconductor device comprising an underlying film, a first electrode formed on the underlying film, a first dielectric film formed on the first electrode, a second electrode formed on the first dielectric film, and a first interconnect including a first conductive portion extending in a stack direction of the first electrode, the first dielectric film and the second electrode, a side surface of the first conductive portion being in contact with one of the first electrode and the second electrode.
摘要翻译：公开了一种半导体器件，包括下面的膜，形成在下面的膜上的第一电极，形成在第一电极上的第一电介质膜，形成在第一电介质膜上的第二电极和第一互连件，第一互连件包括第一导电部分，第一电极的堆叠方向，第一电介质膜和第二电极，第一导电部分的侧表面与第一电极和第二电极中的一个接触。

16. 发明授权

US06614642B1 Capacitor over plug structure 有权
标题翻译：电容器插头结构
公开(公告)号：US06614642B1
公开(公告)日：2003-09-02
申请号：US10065122
申请日：2002-09-19
申请人： Bum-ki Moon , Moto Yabuki , Gerhard Beitel , Nicolas Nagel , Andreas Hilliger , Takamichi Tsuchiya
发明人： Bum-ki Moon , Moto Yabuki , Gerhard Beitel , Nicolas Nagel , Andreas Hilliger , Takamichi Tsuchiya
IPC分类号： H01G4228
CPC分类号： H01L28/75 , H01L21/28568 , H01L28/60 , H01L28/90
摘要： A capacitor over plug (COP) structure is disclosed. The COP avoids the step which is created in conventional COP structures, which adversely impacts the properties of the capacitor. In one embodiment, the step is avoided by providing a plug having upper and lower portions. The upper portion, which is coupled to the bottom electrode of the capacitor, has substantially the same surface area as the bottom electrode. A barrier layer can be provided between the plug and bottom electrode to avoid oxidation of the plug material.
摘要翻译：公开了一种电容器插头（COP）结构。 COP避免了常规COP结构中产生的步骤，这对电容器的性能产生不利影响。在一个实施例中，通过提供具有上部和下部的插塞来避免该步骤。耦合到电容器的底部电极的上部具有与底部电极基本相同的表面积。可以在塞子和底部电极之间提供阻挡层以避免塞子材料的氧化。

17. 发明授权

US08558354B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08558354B2
公开(公告)日：2013-10-15
申请号：US13052143
申请日：2011-03-21
申请人： Yoko Iwakaji , Jun Hirota , Moto Yabuki , Wakana Kai , Hirokazu Ishida , Ichiro Mizushima
发明人： Yoko Iwakaji , Jun Hirota , Moto Yabuki , Wakana Kai , Hirokazu Ishida , Ichiro Mizushima
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/02425 , H01L21/0245 , H01L21/02502 , H01L21/02516 , H01L21/02532 , H01L21/02609 , H01L21/02667 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L29/685 , H01L29/868 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/16 , H01L45/1675
摘要： According to one embodiment, a semiconductor device includes a plurality of silicon films. The plurality of silicon films are disposed on one plane and are made of polysilicon containing an impurity. A crystal orientation of each of the silicon films is a (311) orientation.
摘要翻译：根据一个实施例，半导体器件包括多个硅膜。多个硅膜设置在一个平面上，由含有杂质的多晶硅制成。每个硅膜的晶体取向为（311）取向。

18. 发明申请

US20120235107A1 NONVOLATILE MEMORY DEVICE 失效
标题翻译：非易失性存储器件
公开(公告)号：US20120235107A1
公开(公告)日：2012-09-20
申请号：US13236713
申请日：2011-09-20
申请人： Jun Hirota , Yoko Iwakaji , Moto Yabuki
发明人： Jun Hirota , Yoko Iwakaji , Moto Yabuki
IPC分类号： H01L45/00
CPC分类号： H01L45/04 , H01L27/2409 , H01L27/2481 , H01L45/1233 , H01L45/145 , H01L45/1675
摘要： According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, a pillar, and charge bearing members. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction that intersects the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The charge bearing members contain a negative fixed charge, and provided on side faces of the pillars. The pillars includes a diode film provided with a p-type layer and an n-type layer and a variable resistance film stacked on the diode film. The charge bearing member is disposed on side faces of the p-type layer, and is not disposed on side faces of the n-type layer.
摘要翻译：根据一个实施例，非易失性存储器件包括字线互连层，位线互连层，柱和电荷承载部件。字线互连层包括沿第一方向延伸的多个字线。位线互连层包括沿与第一方向相交的第二方向延伸的多个位线。支柱设置在每个字线和每个位线之间。电荷承载部件包含负的固定电荷，并且设置在支柱的侧面上。支柱包括二极管膜，该二极管膜设置有层叠在二极管膜上的p型层和n型层以及可变电阻膜。电荷承载部件配置在p型层的侧面，不配置在n型层的侧面。

19. 发明申请

US20110227025A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110227025A1
公开(公告)日：2011-09-22
申请号：US12872284
申请日：2010-08-31
申请人： Jun HIROTA , Yoko Iwakaji , Moto Yabuki
发明人： Jun HIROTA , Yoko Iwakaji , Moto Yabuki
IPC分类号： H01L45/00 , H01L29/868 , H01L21/77
CPC分类号： H01L27/1021 , H01L27/101
摘要： According to one embodiment, a semiconductor memory device includes a word line interconnection layer, a bit line interconnection layer and a pillar. The word line interconnection layer includes a plurality of word lines which extend in a first direction. The bit line interconnection layer includes a plurality of bit lines which extend in a second direction crossing over the first direction. The pillar is arranged between each of the word lines and each of the bit lines. The pillar includes a silicon diode and a variable resistance film, and the silicon diode includes a p-type portion and an n-type portion. The word line interconnection layer and the bit line interconnection layer are alternately stacked, and a compressive force is applied to the silicon diode in a direction in which the p-type portion and the n-type portion become closer to each other.
摘要翻译：根据一个实施例，半导体存储器件包括字线互连层，位线互连层和柱。字线互连层包括沿第一方向延伸的多个字线。位线互连层包括沿与第一方向交叉的第二方向延伸的多个位线。支柱布置在每个字线和每个位线之间。支柱包括硅二极管和可变电阻膜，并且硅二极管包括p型部分和n型部分。字线互连层和位线互连层交替堆叠，并且在p型部分和n型部分变得更接近的方向上对硅二极管施加压缩力。

20. 发明授权

US07915156B2 Semiconductor memory device and method for manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07915156B2
公开(公告)日：2011-03-29
申请号：US12391953
申请日：2009-02-24
申请人： Kenji Aoyama , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
发明人： Kenji Aoyama , Eiji Ito , Masahiro Kiyotoshi , Tadashi Iguchi , Moto Yabuki
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/764 , H01L29/66825
摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.
摘要翻译：半导体存储器件具有半导体衬底，在半导体衬底上以预定间隔形成的多个字线，每个字线具有栅极绝缘膜，电荷存储层，第一绝缘膜和控制栅电极，它们被堆叠并且包括位于栅极绝缘膜的高度之上的金属氧化物层，覆盖字线的一侧的第二绝缘膜和字线之间的半导体衬底的表面，并且具有15nm的膜厚度或并且形成在彼此相邻的字线之间的第三绝缘膜，使得低于金属氧化物层的电平的区域具有空腔。

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