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11. 发明申请

US20050156246A1 METHODS OF FORMING STRAINED-SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES 有权
标题翻译：形成应变半导体绝缘体器件结构的方法
公开(公告)号：US20050156246A1
公开(公告)日：2005-07-21
申请号：US11073780
申请日：2005-03-07
申请人： Anthony Lochtefeld , Thomas Langdo , Richard Hammond , Matthew Currie , Eugene Fitzgerald
发明人： Anthony Lochtefeld , Thomas Langdo , Richard Hammond , Matthew Currie , Eugene Fitzgerald
IPC分类号： H01L21/20 , H01L21/336 , H01L21/337 , H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L31/0392
CPC分类号： H01L21/76254 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02505 , H01L21/0251 , H01L21/02521 , H01L21/02532 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/66916 , H01L29/7842 , H01L29/78603 , H01L29/78684 , H01L29/78687
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
摘要翻译：应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

12. 发明授权

US06900094B2 Method of selective removal of SiGe alloys 有权
标题翻译：选择性去除SiGe合金的方法
公开(公告)号：US06900094B2
公开(公告)日：2005-05-31
申请号：US10172542
申请日：2002-06-14
申请人： Richard Hammond , Matthew Currie
发明人： Richard Hammond , Matthew Currie
IPC分类号： H01L21/00 , H01L21/31 , H01L21/311 , H01L21/316 , H01L21/336 , H01L21/469 , H01L21/76 , H01L21/8238 , H01L21/8242 , H01L21/8244 , H01L29/10 , H01L29/78
CPC分类号： H01L29/1054 , H01L21/823807 , H01L29/7833
摘要： A method is disclosed of forming buried channel devices and surface channel devices on a heterostructure semiconductor substrate. In an embodiment, the method includes the steps of providing a structure including a first layer having a first oxidation rate disposed over a second layer having a second oxidation rate wherein the first oxidation rate is greater than the second oxidation rate, reacting said first layer to form a sacrificial layer, and removing said sacrificial layer to expose said second layer.
摘要翻译：公开了在异质结构半导体衬底上形成掩埋沟道器件和表面沟道器件的方法。在一个实施方案中，该方法包括以下步骤：提供包括具有第一氧化速率的第一层的结构，该第一层设置在具有第二氧化速率的第二层上，其中第二氧化速率大于第二氧化速率，使第一层与形成牺牲层，并且去除所述牺牲层以暴露所述第二层。

13. 发明申请

US20050054168A1 Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same 有权
标题翻译：使用具有限定杂质梯度的应变材料层的半导体结构及其制造方法
公开(公告)号：US20050054168A1
公开(公告)日：2005-03-10
申请号：US10972578
申请日：2004-10-25
申请人： Matthew Currie , Anthony Lochtefeld , Richard Hammond , Eugene Fitzgerald
发明人： Matthew Currie , Anthony Lochtefeld , Richard Hammond , Eugene Fitzgerald
IPC分类号： H01L21/20 , H01L21/02 , H01L21/338 , H01L27/12 , H01L29/10 , H01L29/36 , H01L29/778 , H01L29/78 , H01L29/786 , H01L29/812 , H01L21/336
CPC分类号： H01L29/1054 , H01L29/105 , H01L29/161 , H01L29/36 , H01L29/66477 , H01L29/66545 , H01L29/66651 , H01L29/78 , H01L29/7842 , Y10S438/926
摘要： Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
摘要翻译：包括具有无杂质区域的应变材料层的半导体结构和器件及其制造方法。应变材料层的某些区域保持没有可以从半导体的相邻部分相互扩散的杂质。当杂质存在于应变材料层的某些区域中时，器件性能下降。通过采用具有所描述或者根据所描述的步骤制造的特征的半导体结构和器件（例如，场效应晶体管或“FET”），器件操作被增强。

14. 发明申请

US20050035389A1 Dynamic random access memory trench capacitors 有权
标题翻译：动态随机存取存储器沟槽电容器
公开(公告)号：US20050035389A1
公开(公告)日：2005-02-17
申请号：US10947909
申请日：2004-09-23
申请人： Mayank Bulsara , Matthew Currie , Anthony Lochtefeld
发明人： Mayank Bulsara , Matthew Currie , Anthony Lochtefeld
IPC分类号： H01L21/8242 , H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L27/10829 , H01L27/1087 , H01L27/10894 , H01L27/10897 , H01L28/40 , H01L29/1054 , H01L29/7849 , H01L29/945
摘要： DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
摘要翻译：尤其是通过将导电材料沉积到沟槽中或掺杂限定沟槽的半导体区域形成的DRAM沟槽电容器。

15. 发明授权

US06583015B2 Gate technology for strained surface channel and strained buried channel MOSFET devices 有权
公开(公告)号：US06583015B2
公开(公告)日：2003-06-24
申请号：US09923207
申请日：2001-08-06
申请人： Eugene A. Fitzgerald , Richard Hammond , Matthew Currie
发明人： Eugene A. Fitzgerald , Richard Hammond , Matthew Currie
IPC分类号： H01L21336
CPC分类号： H01L29/66477 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L21/02664 , H01L21/28194 , H01L21/28211 , H01L21/28238 , H01L29/1054 , H01L29/78 , H01L29/7838 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1−xGex layer on a substrate, a strained channel layer on the relaxed Si1−xGex layer, and a Si1−yGey layer; removing the Si1−yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.

16. 发明申请

US20120104461A1 Semiconductor Heterostructures Having Reduced Dislocation Pile-Ups and Related Methods 有权
标题翻译：具有减少位错堆积和相关方法的半导体异质结构
公开(公告)号：US20120104461A1
公开(公告)日：2012-05-03
申请号：US13348778
申请日：2012-01-12
申请人： Christopher Leitz , Christopher Vineis , Richard Westhoff , Vicky Yang , Matthew Currie
发明人： Christopher Leitz , Christopher Vineis , Richard Westhoff , Vicky Yang , Matthew Currie
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L21/0251 , C30B23/025 , C30B23/066 , C30B25/02 , C30B25/183 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/0262 , H01L21/823807
摘要： Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
摘要翻译：组分梯度半导体层中的位错堆叠被减少或消除，从而导致半导体器件的产量和可制造性的提高。这是通过在组成渐变层的生长和弛豫期间引入具有多个穿透位错基本上均匀分布在其表面上的半导体层作为起始层和/或至少一个中间层来实现的。半导体层可以包括接近半导体层的表面并且穿透位错均匀分布在其中的晶种层。

17. 发明授权

US07368308B2 Methods of fabricating semiconductor heterostructures 有权
标题翻译：制造半导体异质结构的方法
公开(公告)号：US07368308B2
公开(公告)日：2008-05-06
申请号：US11227770
申请日：2005-09-15
申请人： Christopher Vineis , Vicky Yang , Matthew Currie , Richard Westhoff , Christopher Leitz
发明人： Christopher Vineis , Vicky Yang , Matthew Currie , Richard Westhoff , Christopher Leitz
IPC分类号： H01L21/00 , H01L29/06
CPC分类号： H01L21/0251 , C30B23/025 , C30B23/066 , C30B25/02 , C30B25/183 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/0262 , H01L21/823807
摘要： Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
摘要翻译：组分梯度半导体层中的位错堆叠被减少或消除，从而导致半导体器件的产量和可制造性的提高。这是通过在组成渐变层的生长和弛豫期间引入具有多个穿透位错基本上均匀分布在其表面上的半导体层作为起始层和/或至少一个中间层来实现的。半导体层可以包括接近半导体层的表面并且穿透位错均匀分布在其中的晶种层。

18. 发明申请

US20070293009A1 SEMICONDUCTOR STRUCTURES EMPLOYING STRAINED MATERIAL LAYERS WITH DEFINED IMPURITY GRADIENTS AND METHODS FOR FABRICATING SAME 有权
标题翻译：使用定义的污染物等级的应变材料层的半导体结构及其制造方法
公开(公告)号：US20070293009A1
公开(公告)日：2007-12-20
申请号：US11848642
申请日：2007-08-31
申请人： Matthew Currie , Anthony Lochtefeld , Richard Hammond , Eugene Fitzgerald
发明人： Matthew Currie , Anthony Lochtefeld , Richard Hammond , Eugene Fitzgerald
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L29/105 , H01L29/161 , H01L29/36 , H01L29/66477 , H01L29/66545 , H01L29/66651 , H01L29/78 , H01L29/7842 , Y10S438/926
摘要： Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
摘要翻译：包括具有无杂质区域的应变材料层的半导体结构和器件及其制造方法。应变材料层的某些区域保持没有可以从半导体的相邻部分相互扩散的杂质。当杂质存在于应变材料层的某些区域中时，器件性能下降。通过采用具有所描述或者根据所描述的步骤制造的特征的半导体结构和器件（例如，场效应晶体管或“FET”），器件操作被增强。

19. 发明申请

US20070001231A1 Material systems for dielectrics and metal electrodes 审中-公开
标题翻译：电介质和金属电极材料体系
公开(公告)号：US20070001231A1
公开(公告)日：2007-01-04
申请号：US11170341
申请日：2005-06-29
申请人： Matthew Currie
发明人： Matthew Currie
IPC分类号： H01L29/94
CPC分类号： H01L29/78696 , H01L21/28202 , H01L21/823462 , H01L29/4908 , H01L29/518 , H01L29/66181 , H01L29/7833 , H01L29/785
摘要： A structure having a dielectric layer that includes a dielectric material comprising a first metal nitride, and an electrode layer disposed over the dielectric layer, the electrode layer comprising a second metal nitride, with the first metal nitride and the second metal nitride having at least one metal in common. Alternatively, structure has a dielectric layer including a dielectric material comprising a metal oxide, and an electrode layer disposed over the dielectric layer, the electrode layer comprising a metal nitride. The metal oxide and the metal nitride each comprise at least one of a rare earth metal, a group IIIA metal, an alkali metal, an alkaline earth metal, and a transition metal, and the metal oxide and the metal nitride comprise the same metal. An interfacial layer may be disposed under the dielectric layer.
摘要翻译：一种具有电介质层的结构，该电介质层包括包含第一金属氮化物的电介质材料和设置在电介质层上的电极层，该电极层包括第二金属氮化物，第一金属氮化物和第二金属氮化物具有至少一个金属共同点或者，结构具有包括包含金属氧化物的介电材料的电介质层和设置在电介质层上的电极层，该电极层包含金属氮化物。金属氧化物和金属氮化物各自包含稀土金属，IIIA族金属，碱金属，碱土金属和过渡金属中的至少一种，并且金属氧化物和金属氮化物包含相同的金属。界面层可以设置在介电层下面。

20. 发明申请

US20060266997A1 Methods for forming semiconductor structures with differential surface layer thicknesses 审中-公开
标题翻译：用于形成具有差的表面层厚度的半导体结构的方法
公开(公告)号：US20060266997A1
公开(公告)日：2006-11-30
申请号：US11498521
申请日：2006-08-03
申请人： Matthew Currie , Anthony Lochtefeld , Eugene Fitzgerald
发明人： Matthew Currie , Anthony Lochtefeld , Eugene Fitzgerald
IPC分类号： H01L31/00
CPC分类号： H01L21/823807 , H01L21/823412 , H01L27/0922
摘要： A semiconductor structure having a substrate with a surface layer including strained silicon. The surface layer has a first region with a first thickness less than a second thickness of a second region. A gate dielectric layer is disposed over a portion of at least the first surface layer region.
摘要翻译：具有具有包括应变硅的表面层的基板的半导体结构。表面层具有第一厚度小于第二区域的第二厚度的第一区域。栅电介质层设置在至少第一表面层区域的一部分上。

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