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11. 发明申请

US20060125459A1 DC converter with halt mode setting means 有权
标题翻译： DC转换器，具有停止模式设置装置
公开(公告)号：US20060125459A1
公开(公告)日：2006-06-15
申请号：US11350742
申请日：2006-02-10
申请人： Katsuhiko Manabe , Tomonari Katoh , Minoru Sugiyama , Makoto Matsushima , Tadayoshi Ueda
发明人： Katsuhiko Manabe , Tomonari Katoh , Minoru Sugiyama , Makoto Matsushima , Tadayoshi Ueda
IPC分类号： G05F1/40 , G05F1/56
CPC分类号： H02M1/32 , H02M3/156 , H02M2001/0032 , Y02B70/16
摘要： A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.
摘要翻译：公开了一种具有停止模式设置的DC转换器，用于防止过电流的发生，同时减轻电路尺寸的增加，以及用于设置这种停止模式的方法。 DC转换器包括半导体开关，时钟发生器，用于向半导体开关的栅极输出时钟信号，以用于控制半导体开关的接通/关断时间，使得从发电机输出预定功率;以及驱动电路，用于根据暂停模式设定要求将半导体开关切换到连续导通状态，无论时钟信号如何，当半导体开关通常重复响应时钟信号的开/关操作处于其截止状态时。

12. 发明授权

US07953145B2 Pulse width modulation signal generating circuit 有权
标题翻译：脉宽调制信号发生电路
公开(公告)号：US07953145B2
公开(公告)日：2011-05-31
申请号：US12061360
申请日：2008-04-02
申请人： Makoto Matsushima
发明人： Makoto Matsushima
IPC分类号： H03K7/08 , H03K9/08
CPC分类号： H05B33/0818 , H03K7/08 , H05B33/0848 , Y02B20/346
摘要： A PWM signal generating circuit outputs a stable PWM signal for increasing and decreasing a duty ratio at a predetermined rate within a predetermined period without requiring an improvement of a process capacity of a CPU as compared to a conventional PWM signal generating circuit. The PWM signal generating circuit consists of a plurality of circuit elements each of which outputs a digital signal. A first counter circuit periodically changes a PWM signal output therefrom into an active state. A second counter circuit changes the PWM signal, which has been changed into the active state by the first counter circuit, into an inactive state within each cycle. The second counter circuit increases and decreases an active-to-inactive time period from a time when the PWM signal is changed into the active state to a time when the PWM signal is changed into the inactive state.
摘要翻译： PWM信号发生电路输出用于在预定时间内以预定速率增加和减小占空比的稳定PWM信号，而不需要改善CPU的处理能力，而不是传统的PWM信号发生电路。 PWM信号产生电路由多个电路元件组成，每个电路元件输出数字信号。第一计数器电路将从其输出的PWM信号周期性地改变为活动状态。第二计数器电路将已经被第一计数器电路改变为活动状态的PWM信号在每个周期内变为非活动状态。第二计数器电路从PWM信号变为有效状态的时刻到PWM信号变为不活动状态的时刻，增加和减少从有源到非活动时间段。

13. 发明授权

US07408334B2 DC converter with halt mode setting means 失效
标题翻译： DC转换器，具有停止模式设置装置
公开(公告)号：US07408334B2
公开(公告)日：2008-08-05
申请号：US11705584
申请日：2007-02-13
申请人： Katsuhiko Manabe , Tomonari Katoh , Minoru Sugiyama , Makoto Matsushima , Tadayoshi Ueda
发明人： Katsuhiko Manabe , Tomonari Katoh , Minoru Sugiyama , Makoto Matsushima , Tadayoshi Ueda
IPC分类号： G05F1/56
CPC分类号： H02M1/32 , H02M3/156 , H02M2001/0032 , Y02B70/16
摘要： A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.
摘要翻译：公开了一种具有停止模式设置的DC转换器，用于防止过电流的发生，同时减轻电路尺寸的增加，以及用于设置这种停止模式的方法。 DC转换器包括半导体开关，时钟发生器，用于向半导体开关的栅极输出时钟信号，以用于控制半导体开关的接通/关断时间，使得从发电机输出预定功率;以及驱动电路，用于根据暂停模式设定要求将半导体开关切换到连续导通状态，无论时钟信号如何，当半导体开关通常重复响应时钟信号的开/关操作处于其截止状态时。

14. 发明授权

US07372902B2 Pulse with modulation signal generating circuit 失效
标题翻译：具有调制信号发生电路的脉冲
公开(公告)号：US07372902B2
公开(公告)日：2008-05-13
申请号：US10695839
申请日：2003-10-29
申请人： Makoto Matsushima
发明人： Makoto Matsushima
IPC分类号： H03K7/08 , H03K9/08
CPC分类号： H05B33/0818 , H03K7/08 , H05B33/0848 , Y02B20/346
摘要： A PWM signal generating circuit outputs a stable PWM signal for increasing and deceasing a duty ratio at a predetermined rate within a predetermined period without requiring an improvement of a process capacity of a CPU as compared to a conventional PWM signal generating circuit. The PWM signal generating circuit consists of a plurality of circuit elements each of which outputs a digital signal. A first counter circuit periodically changes a PWM signal output therefrom into an active state. A second counter circuit changes the PWM signal, which has been changed into the active state by the first counter circuit, into an inactive state within each cycle. The second counter circuit increases and decreases an active-to-inactive time period from a time when the PWM signal is changed into the active state to a time when the PWM signal is changed into the inactive state.
摘要翻译： PWM信号发生电路输出稳定的PWM信号，用于在预定时间段内以预定速率增加和减少占空比，而不需要改进CPU的处理能力，而不是传统的PWM信号发生电路。 PWM信号产生电路由多个电路元件组成，每个电路元件输出数字信号。第一计数器电路将从其输出的PWM信号周期性地改变为活动状态。第二计数器电路将已经被第一计数器电路改变为活动状态的PWM信号在每个周期内变为非活动状态。第二计数器电路从PWM信号变为有效状态的时刻到PWM信号变为不活动状态的时刻，增加和减少从有源到非活动时间段。

15. 发明申请

US20060001411A1 DC converter with halt mode setting means 失效
公开(公告)号：US20060001411A1
公开(公告)日：2006-01-05
申请号：US11170745
申请日：2005-06-30
申请人： Katsuhiko Manabe , Tomonari Katoh , Minoru Sugiyama , Makoto Matsushima , Tadayoshi Ueda
发明人： Katsuhiko Manabe , Tomonari Katoh , Minoru Sugiyama , Makoto Matsushima , Tadayoshi Ueda
IPC分类号： G05F1/40
CPC分类号： H02M1/32 , H02M3/156 , H02M2001/0032 , Y02B70/16
摘要： A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

16. 发明申请

US20080203933A1 PULSE WIDTH MODULATION SIGNAL GENERATING CIRCUIT 有权
标题翻译：脉冲宽度调制信号发生电路
公开(公告)号：US20080203933A1
公开(公告)日：2008-08-28
申请号：US12061360
申请日：2008-04-02
申请人： Makoto Matsushima
发明人： Makoto Matsushima
IPC分类号： H05B37/02 , H03K7/08
CPC分类号： H05B33/0818 , H03K7/08 , H05B33/0848 , Y02B20/346
摘要： A PWM signal generating circuit outputs a stable PWM signal for increasing and deceasing a duty ratio at a predetermined rate within a predetermined period without requiring an improvement of a process capacity of a CPU as compared to a conventional PWM signal generating circuit. The PWM signal generating circuit consists of a plurality of circuit elements each of which outputs a digital signal. A first counter circuit periodically changes a PWM signal output therefrom into an active state. A second counter circuit changes the PWM signal, which has been changed into the active state by the first counter circuit, into an inactive state within each cycle. The second counter circuit increases and decreases an active-to-inactive time period from a time when the PWM signal is changed into the active state to a time when the PWM signal is changed into the inactive state.
摘要翻译： PWM信号发生电路输出稳定的PWM信号，用于在预定时间段内以预定速率增加和减少占空比，而不需要改进CPU的处理能力，而不是传统的PWM信号发生电路。 PWM信号产生电路由多个电路元件组成，每个电路元件输出数字信号。第一计数器电路将从其输出的PWM信号周期性地改变为活动状态。第二计数器电路将已经被第一计数器电路改变为活动状态的PWM信号在每个周期内变为非活动状态。第二计数器电路从PWM信号变为有效状态的时刻到PWM信号变为不活动状态的时刻，增加和减少从有源到非活动时间段。

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