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11. 发明授权

US08949691B2 Data processing device and data processing method 有权
标题翻译：数据处理装置和数据处理方法
公开(公告)号：US08949691B2
公开(公告)日：2015-02-03
申请号：US13820808
申请日：2011-09-09
申请人： Yuji Shinohara , Makiko Yamamoto , Lui Sakai
发明人： Yuji Shinohara , Makiko Yamamoto , Lui Sakai
IPC分类号： G11C29/00 , H03M13/13 , H03M13/00 , H03M13/03 , H03M13/11 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/35 , H03M13/15
CPC分类号： H03M13/13 , H03M13/036 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H03M13/356 , H03M13/6552
摘要： The present invention relates to a data processing device and a data processing method capable of improving the resistance to data error. In a case where an LDPC code having a code length of 4,320 bits is mapped into 16 signal points, when a code bit of 4×2 bits and the (#i+1)-th bit from the most significant bit of symbol bits of 4×2 bits of two consecutive symbols are bits b#i and y#i, a demultiplexer performs an interchange process in which b0 is allocated to y0, b1 is allocated to y4, b2 is allocated to y1, b3 is allocated to y6, b4 is allocated to y2, b5 is allocated to y5, b6 is allocated to y3, and b7 is allocated to y7 for an LDPC code having a coded rate of 1/2, and b0 is allocated to y0, b1 is allocated to y4, b2 is allocated to y5, b3 is allocated to y2, b4 is allocated to y1, b5 is allocated to y6, b6 is allocated to y3, and b7 is allocated to y7 for an LDPC code having a coded rate of 7/12, 2/3, and 3/4. The present invention, for example, can be applied to a transmission system transmitting an LDPC code and the like.
摘要翻译：本发明涉及能够提高数据误差阻力的数据处理装置和数据处理方法。在具有4,320比特的码长的LDPC码被映射到16个信号点的情况下，当4×2比特的码比特和来自符号比特的最高有效位的（＃i + 1）比特两个连续符号的4×2位是位b＃i和y＃i，解复用器执行其中b0被分配给y0的交换处理，b1被分配给y4，b2被分配给y1，b3被分配给y6，将b4分配给y2，将b5分配给y5，将b6分配给y3，将b7分配给y7，对于编码速率为1/2的LDPC码，将b0分配给y0，将b1分配给y4， b2分配给y5，b3分配给y2，b4分配给y1，b5分配给y6，b6分配给y3，b7分配给y7，对于编码率为7/12的LDPC码，2 / 3和3/4。本发明例如可以应用于传输LDPC码等的传输系统。

12. 发明授权

US08489955B2 Data processing apparatus, data processing method and program 有权
标题翻译：数据处理装置，数据处理方法和程序
公开(公告)号：US08489955B2
公开(公告)日：2013-07-16
申请号：US12743487
申请日：2008-11-26
申请人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
发明人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
IPC分类号： H03M13/00
CPC分类号： H03M13/1165 , H03M13/1185 , H03M13/255 , H03M13/2703 , H03M13/2707 , H03M13/271 , H03M13/6552 , H03M13/6555 , H04L1/0057
摘要： The present invention relates to a data processing apparatus, a data processing method and a program which can improve the tolerance of code bits of an LDPC code to errors.Where two or more bits of an LDPC (Low Density Parity Check) code are set as one symbol and are mapped to 214 or 216 signal points, a column twist interleaver 24 carries out, as a re-arrangement process for re-arranging code bits of an LDPC code such that a plurality of code bits corresponding to the value 1 included in one arbitrary row of a parity check matrix are not included in one symbol, column twist interleave of changing the writing starting position when code bits are written in a column direction of a memory for each column of the memory. The present invention can be applied, for example, to a transmission apparatus for transmitting an LDPC code.
摘要翻译：本发明涉及一种数据处理装置，数据处理方法和程序，其可以将LDPC码的码位的容限提高到错误。当LDPC（低密度奇偶校验）码的两个或多个比特被设置为一个符号并被映射到214或216个信号点时，列扭曲交织器24执行用于重新排列码位的重新排列处理使得与包括在奇偶校验矩阵的一个任意行中的值1相对应的多个码位不包括在一个符号中的LDPC码，当码位被写入列时改变写入起始位置的列扭曲交织存储器的每列的存储器方向。本发明可以应用于例如用于发送LDPC码的发送装置。

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