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11. 发明授权

US07996810B2 System and method for designing a low leakage monotonic CMOS logic circuit 有权
标题翻译：用于设计低泄漏单调CMOS逻辑电路的系统和方法
公开(公告)号：US07996810B2
公开(公告)日：2011-08-09
申请号：US12103038
申请日：2008-04-15
申请人： Kerry Bernstein , Norman J. Rohrer
发明人： Kerry Bernstein , Norman J. Rohrer
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , H03K19/0016 , H03K19/0948
摘要： A computer system for designing a low leakage monotonic CMOS logic circuit. The system performing the computer implements steps of: (a) specifying a reference PFET having its threshold voltage and its gate dielectric thickness and a reference NFET having its threshold voltage and its gate dielectric thickness; (b) synthesizing a schematic circuit design with standard design elements, the standard design elements including one or more reference PFETS and one or more reference NFETs; (c) analyzing one or more circuits for logic stages having predominantly high input logic states or predominantly low input logic states; (d) selecting one or more logic stages determined to have predominantly high input logic states or predominantly low input logic states; and (e) replacing the standard design elements of the selected logic stages with reduced current leakage elements.
摘要翻译：一种用于设计低泄漏单调CMOS逻辑电路的计算机系统。执行计算机的系统实现以下步骤：（a）指定具有其阈值电压及其栅介质厚度的参考PFET和具有其阈值电压及其栅介质厚度的参考NFET; （b）用标准设计元件合成示意电路设计，标准设计元件包括一个或多个参考PFET和一个或多个参考NFET; （c）分析具有主要为高输入逻辑状态或主要为低输入逻辑状态的逻辑级的一个或多个电路; （d）选择确定为具有主要高输入逻辑状态或主要为低输入逻辑状态的一个或多个逻辑级; 和（e）用减少的电流泄漏元件代替所选逻辑级的标准设计元件。

12. 发明授权

US07960245B2 Dual wired integrated circuit chips 有权
公开(公告)号：US07960245B2
公开(公告)日：2011-06-14
申请号：US12029575
申请日：2008-02-12
申请人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Anthony Kendall Stamper
IPC分类号： H01L21/30
CPC分类号： H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/522 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

13. 发明授权

US07882334B2 Processor pipeline architecture logic state retention systems and methods 有权
标题翻译：处理器管道架构逻辑状态保留系统和方法
公开(公告)号：US07882334B2
公开(公告)日：2011-02-01
申请号：US11276236
申请日：2006-02-20
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G06F15/76 , G06F1/00
CPC分类号： G06F9/3869 , G11C27/026
摘要： A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.
摘要翻译：公开了一种用于保持处理器流水线架构的逻辑状态的系统，方法和程序产品。比较器位于处理器流水线架构的两个阶段之间。存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。提供了与早期输出值相同的参考逻辑。逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点处产生逻辑，该逻辑是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态电容器。提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

14. 发明授权

US07859878B2 Design structure for implementing matrix-based search capability in content addressable memory devices 有权
标题翻译：在内容可寻址存储设备中实现基于矩阵的搜索能力的设计结构
公开(公告)号：US07859878B2
公开(公告)日：2010-12-28
申请号：US12110375
申请日：2008-04-28
申请人： Igor Arsovski , Kerry Bernstein
发明人： Igor Arsovski , Kerry Bernstein
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括内容可寻址存储器（CAM）装置，其具有排列成字线方向的存储单元阵列和排列在位线方向上的列，并且配置有比较电路将存储在阵列中的数据与存储在阵列的每一行和列中的数据进行比较，同时在阵列的每一行和列上指示匹配结果，从而产生二维的基于矩阵的数据比较操作。

15. 发明申请

US20100203689A1 finFET TRANSISTOR AND CIRCUIT 有权
标题翻译： finFET晶体管和电路
公开(公告)号：US20100203689A1
公开(公告)日：2010-08-12
申请号：US12762427
申请日：2010-04-19
申请人： Kerry Bernstein , Edward J. Nowak , BethAnn Rainey
发明人： Kerry Bernstein , Edward J. Nowak , BethAnn Rainey
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66795
摘要： A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.
摘要翻译：驱动强度可调谐FinFET，FinFET的驱动强度调谐方法，驱动强度比调谐FinFET电路和FinFET的驱动强度调谐方法，其中FinFET具有至少一个垂直和至少一个成角度的鳍或具有最少一个双门翅和一个分闸门。

16. 发明授权

US07692944B2 3-dimensional integrated circuit architecture, structure and method for fabrication thereof 有权
标题翻译：三维集成电路体系结构及其制造方法
公开(公告)号：US07692944B2
公开(公告)日：2010-04-06
申请号：US12127086
申请日：2008-05-27
申请人： Kerry Bernstein , Paul W. Coteus , Philip G. Emma
发明人： Kerry Bernstein , Paul W. Coteus , Philip G. Emma
IPC分类号： G11C5/02
CPC分类号： H01L27/0688 , H01L21/6835 , H01L21/8221 , H01L27/105 , H01L27/1052 , H01L2221/68359 , H01L2225/06541 , H01L2924/14 , H01L2924/1433 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105
摘要： An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.
摘要翻译：其制造的集成电路设计，结构和方法包括至少一个逻辑器件层和至少两个额外的分开的存储器阵列层。对于设置在其中的特定类型的逻辑设备或存储器件，逻辑器件层和至少两个存储器阵列层中的每一个被独立地优化。优选地还设置在逻辑器件层内的是阵列读出放大器，存储器阵列输出驱动器和类似的高性能电路，否则通常设置在存储器阵列层衬底内。所有层可以独立供电以提供额外的性能增强。

17. 发明申请

US20100052108A1 VERTICAL THROUGH-SILICON VIA FOR A SEMICONDUCTOR STRUCTURE 有权
标题翻译：通过半导体结构的垂直硅
公开(公告)号：US20100052108A1
公开(公告)日：2010-03-04
申请号：US12201580
申请日：2008-08-29
申请人： John E. Barth, JR. , Kerry Bernstein
发明人： John E. Barth, JR. , Kerry Bernstein
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor structure includes at least one silicon substrate having first and second planar surfaces, and at least one through silicon via filled with a conductive material and extending vertically through the first planar surface of the at least one silicon substrate to the second planar surface thereof. The through silicon via forms a vertical interconnection between a plurality of electronic circuits and an amount of dielectric insulation surrounding the through silicon via is varied based on a defined function of the through silicon via.
摘要翻译：半导体结构包括具有第一和第二平面表面的至少一个硅衬底，以及填充有导电材料并且至少穿过至少一个硅衬底的第一平坦表面垂直延伸到其第二平坦表面的至少一个穿硅通孔。穿通硅通孔在多个电子电路之间形成垂直互连，并且围绕穿过硅通孔的绝缘绝缘体的量基于硅通孔的限定功能而变化。

18. 发明申请

US20100052100A1 DEEP TRENCH ELECTROSTATIC DISCHARGE (ESD) PROTECT DIODE FOR SILICON-ON-INSULATOR (SOI) DEVICES 有权
标题翻译：用于硅绝缘体（SOI）器件的深度放电静电放电（ESD）保护二极管
公开(公告)号：US20100052100A1
公开(公告)日：2010-03-04
申请号：US12201462
申请日：2008-08-29
申请人： John E. Barth, JR. , Kerry Bernstein
发明人： John E. Barth, JR. , Kerry Bernstein
IPC分类号： H01L29/8605 , H01L21/02
CPC分类号： H01L29/861 , H01L21/761 , H01L21/76264 , H01L23/535 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure is disclosed. The semiconductor structure includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.
摘要翻译：公开了半导体结构。半导体结构包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区域和第一极性类型的扩散区域的掩埋绝缘体层的顶部上的有源半导体层设置在掩埋绝缘体层正下方并形成导电路径的第二极性类型的带区域，设置在本体衬底中并与带区接触的第二极性类型的阱区，填充有导电的深沟槽设置在阱区内的第一极性类型的材料以及由深沟槽的下部和阱区之间的接合部限定的静电放电（ESD）保护二极管。

19. 发明授权

US07642813B2 Error correcting logic system 有权
标题翻译：错误校正逻辑系统
公开(公告)号：US07642813B2
公开(公告)日：2010-01-05
申请号：US11850857
申请日：2007-09-06
申请人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
发明人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
IPC分类号： H03K19/20 , H03K19/094 , H03K19/003
CPC分类号： H03K19/007
摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.
摘要翻译：本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。该系统适用于动态或静态逻辑系统。该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。此外，提供了在设计过程中使用的机器可读介质中体现的设计结构，并且包括这种纠错逻辑系统。

20. 发明申请

US20090141527A1 APPARATUS AND METHOD FOR IMPLEMENTING MATRIX-BASED SEARCH CAPABILITY IN CONTENT ADDRESSABLE MEMORY DEVICES 有权
标题翻译：在内容可寻址存储器件中实现基于矩阵的搜索能力的装置和方法
公开(公告)号：US20090141527A1
公开(公告)日：2009-06-04
申请号：US11949063
申请日：2007-12-03
申请人： Igor Arsovski , Kerry Bernstein
发明人： Igor Arsovski , Kerry Bernstein
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) device includes an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation.
摘要翻译：一种内容可寻址存储器（CAM）装置，包括排列成字线方向的存储单元阵列和排列在位线方向上的列，以及比较电路，被配置为将呈现给阵列的数据与存储在每行和列中的数据进行比较并且同时指示阵列的每一行和列上的匹配结果，从而导致二维的基于矩阵的数据比较操作。

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