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11. 发明授权

US06830966B2 Fully silicided NMOS device for electrostatic discharge protection 失效
标题翻译：用于静电放电保护的全硅化NMOS器件
公开(公告)号：US06830966B2
公开(公告)日：2004-12-14
申请号：US10170248
申请日：2002-06-12
申请人： Jun Cai , Keng Foo Lo
发明人： Jun Cai , Keng Foo Lo
IPC分类号： H01L21336
CPC分类号： H01L29/0847 , H01L27/0266 , H01L29/1083 , H01L29/7833 , Y10S257/90
摘要： A device and method are described for forming a grounded gate NMOS (GGNMOS) device used to provide protection against electrostatic discharge (ESD) in an integrated circuit (IC). The device is achieved by adding n-wells below the source and drain regions. By tailoring the dopant concentration profiles of the p-well and n-wells provided in the fabrication process, peak dopant concentrations are moved below the silicon surface. This moves ESD conduction deeper into the IC where thermal conductivity is improved, thereby avoiding thermal damage occurring with surface conduction. The device does not require a salicidation block or additional implantation and uses standard NMOS fabrication processing steps, making it advantageous over prior art solutions.
摘要翻译：描述了用于形成用于提供集成电路（IC）中的静电放电（ESD）保护的接地栅极NMOS（GGNMOS）器件的器件和方法。该器件通过在源极和漏极区域下方添加n阱来实现。通过调整在制造过程中提供的p阱和n阱的掺杂浓度分布，峰值掺杂剂浓度移动到硅表面以下。这将ESD传导更深地传导到IC中，其中导热性得到改善，从而避免了表面传导引起的热损伤。该器件不需要一个盐化阻滞或额外的植入，并且使用标准的NMOS制造处理步骤，使其优于现有技术的解决方案。

12. 发明授权

US06555878B2 Umos-like gate-controlled thyristor structure for ESD protection 有权
标题翻译：类似Umos的栅极控制晶闸管结构，用于ESD保护
公开(公告)号：US06555878B2
公开(公告)日：2003-04-29
申请号：US10233764
申请日：2002-09-03
申请人： Jun Song , Guang ping Hua , Keng-Foo Lo
发明人： Jun Song , Guang ping Hua , Keng-Foo Lo
IPC分类号： H01L2362
CPC分类号： H01L27/0262 , H01L29/7436
摘要： Described is a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+/n+ diffusion (anode). A latchup immune circuit is achieved by creating a U-shaped gate structure which is lined with a thick gate oxide—similar to a field oxide—under the poly gate.
摘要翻译：描述了具有用于IC器件中的ESD保护电路的U形门（UMOS）的MOS栅极控制SCR（UGSCR）结构，其与浅沟槽隔离（STI）和自对准硅化物（自对准硅）制造技术相兼容。 UMOS门位于p基板中，并且被两侧的n阱包围。邻近UMOS门的一侧，形成跨越第一n阱的第一n +扩散。 n +扩散以及旁边扩散的p +拾取器形成SCR（晶闸管）的阴极。在UMOS门的另一侧附近，在第二n阱中形成第二n +和p +扩散。第二个n +和p +扩散与UMOS门一起形成SCR的阳极和要保护的电路的输入端。 SCR由第一n +扩散/ n阱（阴极），p衬底，第二n阱和第二p + / n +扩散（阳极）形成。闭锁免疫电路通过在聚栅下形成一个衬有厚栅极氧化物（类似于场氧化物）的U形门结构来实现。

13. 发明授权

US06458632B1 UMOS-like gate-controlled thyristor structure for ESD protection 失效
标题翻译：类似UMOS的门控晶闸管结构，用于ESD保护
公开(公告)号：US06458632B1
公开(公告)日：2002-10-01
申请号：US09814478
申请日：2001-03-14
申请人： Jun Song , Guang Ping Hua , Keng-Foo Lo
发明人： Jun Song , Guang Ping Hua , Keng-Foo Lo
IPC分类号： H01L21332
CPC分类号： H01L27/0262 , H01L29/7436
摘要： Described is a method of creating a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+/n+ diffusion (anode). A latchup immune circuit is achieved by creating a U-shaped gate structure which is lined with a thick gate oxide—similar to a field oxide—under the poly gate.
摘要翻译：描述了一种用于在IC器件中的用于ESD保护电路的U形栅极（UMOS）的MOS栅极控制SCR（UGSCR）结构的方法，其与浅沟槽隔离（STI）和自对准硅化物（STI）兼容自杀）制造技术。 UMOS门位于p基板中，并且被两侧的n阱包围。邻近UMOS门的一侧，形成跨越第一n阱的第一n +扩散。 n +扩散以及旁边扩散的p +拾取器形成SCR（晶闸管）的阴极。在UMOS门的另一侧附近，在第二n阱中形成第二n +和p +扩散。第二个n +和p +扩散与UMOS门一起形成SCR的阳极和要保护的电路的输入端。 SCR由第一n +扩散/ n阱（阴极），p衬底，第二n阱和第二p + / n +扩散（阳极）形成。闭锁免疫电路通过在聚栅下形成一个衬有厚栅极氧化物（类似于场氧化物）的U形门结构来实现。

14. 发明授权

US06417541B1 ESD protection network with field oxide device and bonding pad 失效
标题翻译： ESD保护网络与场氧化物和接合焊盘
公开(公告)号：US06417541B1
公开(公告)日：2002-07-09
申请号：US09759492
申请日：2001-01-12
申请人： Jun Cai , Keng Foo Lo
发明人： Jun Cai , Keng Foo Lo
IPC分类号： H01L2362
CPC分类号： H01L27/0277
摘要： An electrostatic discharge protection structure is provided with a dielectric gate, source and drain contacts, and a semiconductor substrate. The semiconductor substrate is of a first conductivity type having the dielectric gate disposed partially on its surface. The source and drain contacts are connected to source and drain diffusion regions of a second conductivity type separated by the dielectric gate. Deep source and drain wells of the second conductivity type respectively disposed under the source and drain diffusion regions define a channel region of the first conductivity type. The channel region is doped so that the surface breakdown voltage is exceeded before the subsurface depletion region punch-through voltage is exceeded between the deep source and drain wells upon an electrostatic discharge at the drain contact.
摘要翻译：静电放电保护结构设置有电介质栅极，源极和漏极触点以及半导体衬底。半导体衬底是第一导电类型，其中介电栅极部分地设置在其表面上。源极和漏极触点连接到由电介质栅极隔开的第二导电类型的源极和漏极扩散区域。分别设置在源极和漏极扩散区域下方的第二导电类型的深源极和漏极阱限定第一导电类型的沟道区。在漏极接触处的静电放电之后，在深源极和漏极阱之间超过地下耗尽区穿透电压之前，掺杂沟道区域，使得超过表面击穿电压。

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