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11. 发明授权

US5574450A Synchronization adder circuit 失效
标题翻译：同步加法器电路
公开(公告)号：US5574450A
公开(公告)日：1996-11-12
申请号：US302029
申请日：1994-09-09
申请人： Katsuhiko Hiramatsu , Kazunori Inogai , Kimihiko Ishikawa
发明人： Katsuhiko Hiramatsu , Kazunori Inogai , Kimihiko Ishikawa
IPC分类号： H04J1/00 , H04L5/06 , H04L7/02 , H04L27/22 , H04L27/38 , H03M1/48
CPC分类号： H04L7/0054 , H04L5/06
摘要： A synchronization adder circuit for digital data communication includes an A/D converter, a waveform-shaping circuit, a square circuit, a low-pass filter, and an adder. The A/D converter samples at given sampling points in time per sampling cycle a received signal transmitted through a plurality of subcarriers to digitize sampled values to provide digital signals. The waveform-shaping circuit then waveform-shapes the digital signals from said A/D converter without decomposing them with respect to each subcarrier. The square circuit squares the output signals from the waveform-shaping circuit. The low-pass filter removes a given high-frequency component from output signals from the square circuit. The adder adds values of output signals from the low-pass filter at each sapling point for preselected sapling cycles to determine the samples suitable for reproduction of original data.
摘要翻译：用于数字数据通信的同步加法器电路包括A / D转换器，波形整形电路，平方电路，低通滤波器和加法器。 A / D转换器在每个采样周期的给定采样点采样时间，通过多个子载波传输的接收信号以数字化采样值以提供数字信号。然后，波形整形电路对来自所述A / D转换器的数字信号进行波形整形，而不会相对于每个子载波分解它们。平方电路对来自波形整形电路的输出信号进行平方。低通滤波器从平方电路的输出信号中去除给定的高频分量。加法器在预选的树苗周期中，在每个树苗点处从低通滤波器输出的信号值，以确定适合于再现原始数据的样本。

12. 发明授权

US08559347B2 Method and apparatus for intermittent communication 有权
标题翻译：间歇通信的方法和装置
公开(公告)号：US08559347B2
公开(公告)日：2013-10-15
申请号：US13030938
申请日：2011-02-18
申请人： Jun Hirano , Takashi Aramaki , Kazunori Inogai
发明人： Jun Hirano , Takashi Aramaki , Kazunori Inogai
IPC分类号： G08C17/00
CPC分类号： H04W52/0216 , H04L1/1664 , H04W76/28 , Y02D70/142
摘要： When an intermittent communication mode is entered, a check period and intermittent reception mode period thereof are determined and the intermittent reception mode is reentered through an ignored process, that is, when the intermittent reception mode is entered, the check period and intermittent reception mode period are determined in overhead 101 thereof and data 102, 103 is transmitted/received thereafter through an ignored process.
摘要翻译：当进入间歇通信模式时，确定检查周期和间歇接收模式周期，并且通过忽略处理，即当进入间歇接收模式时，检查周期和间歇接收模式周期重新启动间歇接收模式在其开销101中确定，并且之后通过忽略的处理来发送/接收数据102,103。

13. 发明授权

US08363608B2 Sequence allocating method and sequence allocating apparatus 有权
标题翻译：序列分配方法和序列分配装置
公开(公告)号：US08363608B2
公开(公告)日：2013-01-29
申请号：US12442497
申请日：2007-09-28
申请人： Daichi Imamura , Takashi Iwai , Kazunori Inogai , Sadaki Futagi , Atsushi Matsumoto
发明人： Daichi Imamura , Takashi Iwai , Kazunori Inogai , Sadaki Futagi , Atsushi Matsumoto
IPC分类号： H04W4/00
CPC分类号： H04W74/0833 , H04B1/707 , H04B1/7083 , H04B2201/70702 , H04B2201/70713 , H04J13/0062 , H04J13/102 , H04J13/22 , H04L5/0048 , H04L23/02 , H04L27/2613 , H04W72/04 , H04W72/0446 , H04W72/0453 , H04W74/0875
摘要： A sequence allocating method and a sequence allocating apparatus wherein in a system where a plurality of different Zadoff-Chu sequences or GCL sequences are allocated to a single cell, the arithmetic amount and circuit scale of a correlating circuit at a receiving end can be reduced. According to these method and apparatus, in ST201, a counter (a) and a number (p) of current sequence allocations are initialized, and in ST202, it is determined whether the number (p) of current sequence allocations is coincident with a number (K) of allocations to one cell. In ST203, it is determined whether the number (K) of allocations to the one cell is odd or even. If K is even, in ST204-ST206, sequence numbers (r=a and r=N−a), which are not currently allocated, are combined and then allocated. If K is odd, in ST207-ST212, for sequences that cannot be paired, one of sequence numbers (r=a and r=N−a), which are not currently allocated, is allocated.
摘要翻译：一种序列分配方法和序列分配装置，其中在将多个不同的Zadoff-Chu序列或GCL序列分配给单个小区的系统中，可以减少接收端的相关电路的算术量和电路规模。根据这些方法和装置，在ST201中，初始化当前序列分配的计数器（a）和数量（p），在ST202中，确定当前序列分配的数量（p）是否与数字（K）到一个单元的分配。在ST203中，确定对一个单元的分配的数量（K）是奇数还是偶数。如果K是偶数，则在ST204-ST206中，组合然后分配未被分配的序列号（r = a和r = N-a）。如果K是奇数，则在ST207-ST212中，对于不能配对的序列，分配未分配的序列号（r = a和r = N-a）中的一个。

14. 发明申请

US20130010726A1 SEQUENCE ALLOCATING METHOD AND SEQUENCE ALLOCATING APPARATUS 有权
公开(公告)号：US20130010726A1
公开(公告)日：2013-01-10
申请号：US13614334
申请日：2012-09-13
申请人： Daichi Imamura , Takashi Iwai , Kazunori Inogai , Sadaki Futagi , Atsushi Matsumoto
发明人： Daichi Imamura , Takashi Iwai , Kazunori Inogai , Sadaki Futagi , Atsushi Matsumoto
IPC分类号： H04W72/02
CPC分类号： H04W74/0833 , H04B1/707 , H04B1/7083 , H04B2201/70702 , H04B2201/70713 , H04J13/0062 , H04J13/102 , H04J13/22 , H04L5/0048 , H04L23/02 , H04L27/2613 , H04W72/04 , H04W72/0446 , H04W72/0453 , H04W74/0875
摘要： A sequence allocating method and apparatus wherein in a system where a plurality of different Zadoff-Chu sequences or GCL sequences are allocated to a single cell, the arithmetic amount and circuit scale of a correlating circuit at a receiving end can be reduced. In ST201, a counter (a) and a number (p) of current sequence allocations are initialized, and in ST202, it is determined whether the number (p) of current sequence allocations is coincident with a number (K) of allocations to one cell. In ST203, it is determined whether the number (K) of allocations to the one cell is odd or even. If K is even, in ST204-ST206, sequence numbers (r=a and r=N−a), which are not currently allocated, are combined and then allocated. If K is odd, in ST207-ST212, for sequences that cannot be paired, one of sequence numbers (r=a and r=N−a), which are not currently allocated, is allocated.

15. 发明申请

US20130003686A1 SEQUENCE ALLOCATING METHOD AND SEQUENCE ALLOCATING APPARATUS 有权
公开(公告)号：US20130003686A1
公开(公告)日：2013-01-03
申请号：US13614417
申请日：2012-09-13
申请人： Daichi Imamura , Takashi Iwai , Kazunori Inogai , Sadaki Futagi , Atsushi Matsumoto
发明人： Daichi Imamura , Takashi Iwai , Kazunori Inogai , Sadaki Futagi , Atsushi Matsumoto
IPC分类号： H04W72/00 , H04W74/08
CPC分类号： H04W74/0833 , H04B1/707 , H04B1/7083 , H04B2201/70702 , H04B2201/70713 , H04J13/0062 , H04J13/102 , H04J13/22 , H04L5/0048 , H04L23/02 , H04L27/2613 , H04W72/04 , H04W72/0446 , H04W72/0453 , H04W74/0875
摘要： A sequence allocating method and apparatus wherein in a system where a plurality of different Zadoff-Chu sequences or GCL sequences are allocated to a single cell, the arithmetic amount and circuit scale of a correlating circuit at a receiving end can be reduced. In ST201, a counter (a) and a number (p) of current sequence allocations are initialized, and in ST202, it is determined whether the number (p) of current sequence allocations is coincident with a number (K) of allocations to one cell. In ST203, it is determined whether the number (K) of allocations to the one cell is odd or even. If K is even, in ST204-ST206, sequence numbers (r=a and r=N−a), which are not currently allocated, are combined and then allocated. If K is odd, in ST207-ST212, for sequences that cannot be paired, one of sequence numbers (r=a and r=N−a), which are not currently allocated, is allocated.

16. 发明授权

US08085724B2 Sequence report method and sequence report device 有权
标题翻译：序列报告方法和序列报告装置
公开(公告)号：US08085724B2
公开(公告)日：2011-12-27
申请号：US12531864
申请日：2008-03-18
申请人： Daichi Imamura , Takashi Iwai , Kazunori Inogai , Sadaki Futagi , Atsushi Matsumoto
发明人： Daichi Imamura , Takashi Iwai , Kazunori Inogai , Sadaki Futagi , Atsushi Matsumoto
IPC分类号： H04W4/00
CPC分类号： H04W72/0446 , H04J13/0062 , H04J13/0066 , H04J13/22 , H04J2013/0096 , H04L5/0053 , H04W72/005 , H04W72/0413 , H04W72/042 , H04W72/0466
摘要： Disclosed are a sequence report method and a sequence report device for reducing a signaling amount for reporting a Zadoff-Chu sequence or a GCL sequence allocated for a cell. Indexes starting at 1 are correlated to different ZC sequences and are allocated for cells so that the indexes are continuous. When such ZC sequences are reported from BS to UE, a start index indicating the start of the continuous indexes is combined with the number of allocated sequences and they are reported as allocation sequence information by a report channel. The UE and the BS share the correlation between the ZC sequences and the indexes and the UE identifies a usable sequence number according to the correlation and the allocation sequence information reported from the BS.
摘要翻译：公开了一种用于减少用于报告分配给小区的Zadoff-Chu序列或GCL序列的信令量的序列报告方法和序列报告装置。从1开始的索引与不同的ZC序列相关，并且被分配给单元，使得索引是连续的。当从BS向UE报告这样的ZC序列时，将指示连续索引的开始的开始索引与分配的序列的数量组合，并且通过报告信道被报告为分配序列信息。 UE和BS共享ZC序列和索引之间的相关性，并且UE根据从BS报告的相关性和分配顺序信息来标识可用序列号。

17. 发明申请

US20060094365A1 Channel simulator and wireless apparatus evaluation method 审中-公开
标题翻译：通道模拟器和无线设备评估方法
公开(公告)号：US20060094365A1
公开(公告)日：2006-05-04
申请号：US10539090
申请日：2003-12-24
申请人： Kazunori Inogai , Daichi Imamura , Masayuki Hoshino , Genichiro Ota
发明人： Kazunori Inogai , Daichi Imamura , Masayuki Hoshino , Genichiro Ota
IPC分类号： H04B17/00 , H03C1/62
CPC分类号： H04B17/0087 , H04B17/336
摘要： An output signal of digital baseband processing section 41 is directly input, and receiver noise adding section 103 adds receiver noise simulating the SNR variation due to fading to the signal while keeping an entire signal level constant in single-path channel simulation, while in multipath channel simulation, instantaneous variation adding section 101 and short-term interval variation adding section 102 add only amplitude variations to respective signals of paths, and automatic gain control section 104 keeps a level of the path-combined signal constant, whereby it is possible to evaluate channel performance of digital baseband processing section 41 without waiting for development of radio circuit 53, i.e. without an AGC circuit and AFC circuit in reception system 50.
摘要翻译：数字基带处理部分41的输出信号被直接输入，并且接收机噪声加法部分103将在衰落信号中模拟SNR变化的接收机噪声添加到信号，同时在单路信道模拟中保持整个信号电平恒定，而在多径信道仿真，瞬时变化加法部分101和短期间隔变化加法部分102仅对路径的各个信号增加幅度变化，并且自动增益控制部分104保持路径组合信号的电平恒定，从而可以评估信道而无需等待无线电电路53的开发，即在接收系统50中没有AGC电路和AFC电路的数字基带处理部分41的性能。

18. 发明授权

US06236688B1 Receiving circuit 有权
标题翻译：接收电路
公开(公告)号：US06236688B1
公开(公告)日：2001-05-22
申请号：US09258402
申请日：1999-02-26
申请人： Gen-ichiro Ohta , Kazunori Inogai , Fujio Sasaki
发明人： Gen-ichiro Ohta , Kazunori Inogai , Fujio Sasaki
IPC分类号： H03D318
CPC分类号： H04B1/0032 , H03D1/2245 , H03D7/165 , H03D2200/0047 , H03D2200/005 , H03D2200/0082 , H03F3/45475 , H03F3/50 , H03F2200/537 , H04B1/0003 , H04B1/123 , H04B1/26 , H04B5/0093 , Y02D70/40 , Y02D70/42
摘要： A receiving circuit mainly available in a digital modulation type communication system having a plurality of channels, which is capable of reducing power in a receiving system, simplifying the circuit and reducing the power consumption. Upside and downside frequencies corresponding to a central value between channels are separately supplied from a local frequency signal generating circuit 4 to first and second frequency converting circuits 2, 3 so that two output signals are developed with respect to one of a desired wave, upside channel and downside channel. The desired wave present in common in the first and second frequency converting circuits 2, 3 is extracted in a common wave extracting circuit 5, and a frequency offset of &ohgr;o existing in the output of the common wave extracting circuit 5 is removed a frequency offset circuit 6 and further an unnecessary frequency component is filtered by a filter 8. In addition, the common wave extracting circuit 5 has transformers and, using its inductances, raises the difference between the common wave and the non-common wave within the circuit to more than two times that of a prior art.
摘要翻译：主要可用于具有多个信道的数字调制型通信系统中的接收电路，其能够降低接收系统的功率，简化电路并降低功耗。对应于通道之间的中心值的上升和下降频率从本地频率信号发生电路4分别提供给第一和第二频率转换电路2,3，使得两个输出信号相对于所需波形，上行通道和下行通道。在公共波提取电路5中提取在第一和第二频率转换电路2,3中共同存在的期望的波，并且公共波提取电路5的输出中存在的ωω的频率偏移被去除频率偏移电路此外，公共波提取电路5还具有变压器，并且使用其电感将电路内的公共波和非公共波之间的差异提高到超过是现有技术的两倍。

19. 发明授权

US5848100A Frequency conversion and modulation circuits 失效
标题翻译：变频调制电路
公开(公告)号：US5848100A
公开(公告)日：1998-12-08
申请号：US653841
申请日：1996-05-28
申请人： Kazunori Inogai
发明人： Kazunori Inogai
IPC分类号： H03C1/00 , H03D7/00 , H03H17/04 , H03H7/30
CPC分类号： H03H17/0671 , H03C1/00 , H03D7/00
摘要： In a frequency conversion circuit and a modulation circuit, a filter having an impulse response (HB(z); HL(z)) corresponding to a rectangular pulse wave multiplied by a cosine wave of f.sub.3 /4 is a band pass type filter having a center frequency of f.sub.3 /4, and the transfer function H(z) of the filter is expressed in the form of a sum of series. When a numerator part of the transfer function is arranged to be processed with a low-speed sampling frequency f.sub.2 and a denominator part is to be processed with a high-speed sampling frequency f.sub.3 (=L.times.f.sub.2, L: odd number), the circuit can be made to have an adjustment-free structure and small in size. Further, when an output of processing of the numerator part based on the low-speed sampling frequency f.sub.2 is subjected to a D/A conversion while processing of the denominator part based on the high-speed f.sub.3 is implemented by a switched capacitor circuit, power consumption can be reduced.
摘要翻译：在频率转换电路和调制电路中，对应于乘以f3 / 4的余弦波的矩形脉冲波的脉冲响应（HB（z）; HL（z））的滤波器是带通滤波器，具有 f3 / 4的中心频率和滤波器的传递函数H（z）以串联的形式表示。当传递函数的分子部分被布置为以低速采样频率f2进行处理时，以高速采样频率f3（= Lxf2，L：奇数）处理分母部分时，电路可以使其具有无调整的结构，体积小。此外，当基于低速采样频率f2的分子部分的处理输出进行D / A转换，而通过开关电容电路实现基于高速f3的分母部分的处理时，功率消费可以减少。

20. 发明授权

US08730901B2 Sequence allocating method and sequence allocating apparatus 有权
公开(公告)号：US08730901B2
公开(公告)日：2014-05-20
申请号：US13614334
申请日：2012-09-13
申请人： Daichi Imamura , Takashi Iwai , Kazunori Inogai , Sadaki Futagi , Atsushi Matsumoto
发明人： Daichi Imamura , Takashi Iwai , Kazunori Inogai , Sadaki Futagi , Atsushi Matsumoto
IPC分类号： H04W72/02 , H04W72/04
CPC分类号： H04W74/0833 , H04B1/707 , H04B1/7083 , H04B2201/70702 , H04B2201/70713 , H04J13/0062 , H04J13/102 , H04J13/22 , H04L5/0048 , H04L23/02 , H04L27/2613 , H04W72/04 , H04W72/0446 , H04W72/0453 , H04W74/0875
摘要： A sequence allocating method and apparatus wherein in a system where a plurality of different Zadoff-Chu sequences or GCL sequences are allocated to a single cell, the arithmetic amount and circuit scale of a correlating circuit at a receiving end can be reduced. In ST201, a counter (a) and a number (p) of current sequence allocations are initialized, and in ST202, it is determined whether the number (p) of current sequence allocations is coincident with a number (K) of allocations to one cell. In ST203, it is determined whether the number (K) of allocations to the one cell is odd or even. If K is even, in ST204-ST206, sequence numbers (r=a and r=N−a), which are not currently allocated, are combined and then allocated. If K is odd, in ST207-ST212, for sequences that cannot be paired, one of sequence numbers (r=a and r=N−a), which are not currently allocated, is allocated.

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