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11. 发明申请

US20070187798A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070187798A1
公开(公告)日：2007-08-16
申请号：US11611493
申请日：2006-12-15
申请人： Satoshi RITTAKU , Kazuhiro Shimizu
发明人： Satoshi RITTAKU , Kazuhiro Shimizu
IPC分类号： H01L21/336 , H01L29/00
CPC分类号： H01L21/823857 , H01L21/823462 , H01L21/823475 , H01L21/823481 , H01L21/823871 , H01L21/823878 , H01L27/0922 , H01L29/404 , H01L29/42368 , H01L29/66681
摘要： A semiconductor device including a high voltage element and a low voltage element, including: a semiconductor substrate having high voltage element region where the high voltage element is formed, and a low voltage element region where the low voltage element is formed; a first LOCOS isolation structure disposed in the high voltage element region; and a second LOCOS isolation structure disposed in the low voltage element region, wherein the first LOCOS isolation structure includes a LOCOS oxide film formed on a surface of the semiconductor substrate and a CVD oxide film formed on the LOCOS oxide film, and the second LOCOS isolation structure includes a LOCOS oxide film.
摘要翻译：一种包括高电压元件和低电压元件的半导体器件，包括：具有形成高电压元件的高电压元件区域的半导体衬底和形成低电压元件的低电压元件区域; 设置在所述高电压元件区域中的第一LOCOS隔离结构; 以及设置在所述低电压元件区域中的第二LOCOS隔离结构，其中所述第一LOCOS隔离结构包括形成在所述半导体衬底的表面上的LOCOS氧化物膜和形成在所述LOCOS氧化物膜上的CVD氧化膜，以及所述第二LOCOS隔离结构包括LOCOS氧化物膜。

12. 发明授权

US07190034B2 Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage 有权
标题翻译：半导体器件能够避免浮动偏移电压的负变化引起的闭锁故障
公开(公告)号：US07190034B2
公开(公告)日：2007-03-13
申请号：US11229724
申请日：2005-09-20
申请人： Kazunari Hatade , Hajime Akiyama , Kazuhiro Shimizu
发明人： Kazunari Hatade , Hajime Akiyama , Kazuhiro Shimizu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/761 , H01L27/0921 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p+-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p+-type impurity region (33) and the PMOS (15), an n+-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n+-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).
摘要翻译：提供一种半导体器件，其能够避免由高压侧浮动偏置电压（VS）的负变化引起的故障和闭锁故障。在n型杂质区（28）的上表面中，在NMOS（14）和PMOS（15）之间形成有与p型杂质区（33）接触的p + p型井（29）。电极（41）位于p + +型杂质区域（33）上，电极（41）连接到高电压侧浮置偏移电压（VS）。 p型+杂质区域（33）的杂质浓度比p型阱（29）高，比p型阱（29）浅。在p + + / - 型杂质区域（33）和PMOS（15）之间，形成n + +型杂质区域（32）的上表面 n型杂质区（28）。电极（40）位于n + + +型杂质区（32）上，电极（40）连接到高压侧浮动电源绝对电压（VB）。

13. 发明授权

US07122432B2 Non-volatile semiconductor memory device and manufacturing method thereof 失效
公开(公告)号：US07122432B2
公开(公告)日：2006-10-17
申请号：US10956109
申请日：2004-10-04
申请人： Kazuhiro Shimizu , Yuji Takeuchi
发明人： Kazuhiro Shimizu , Yuji Takeuchi
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A non-volatile semiconductor memory device with a small variation in capacitance-coupling to the stacked gate for memory miniaturization. The device has a memory cell array in which memory cells are arranged in array. Each cell has a first gate and a second gate on a semiconductor substrate. The first gate is formed, via a first gate insulating film, on each of device forming regions isolated by device-isolating insulating films. The second gate is formed on the first gate via a second gate insulating film. The first gate is patterned so that its portion is overlapped on the isolation insulating film from the device forming region. A protective insulating film is provided on the isolation film between the device forming regions and in the vicinity of the first gate. A charge-storage layer of each memory cell has at least two stacked conductive layers with a small isolation width at a low aspect ratio for burying isolation insulating films for high density, to easily fabricate in low cost. The side face of the lowest conductive layer meets the side portion of the isolation region. The highest conductive layer has the same width as or is wider than the lowest conductive layer. The first conductive layer is thin for decrease in aspect ratio for burying the insulating film. The second conductive layer has a specific thickness for attaining a desired capacitance between it and the control gate. The highest layer may be formed in self-alignment with the isolation region and stretched out by isotropic-etching.

14. 发明授权

US07109547B2 Non-volatile semiconductor memory device having memory cell array suitable for high density and high integration 失效
公开(公告)号：US07109547B2
公开(公告)日：2006-09-19
申请号：US11305216
申请日：2005-12-19
申请人： Kazuhiro Shimizu , Fumitaka Arai
发明人： Kazuhiro Shimizu , Fumitaka Arai
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L29/42324 , H01L2924/0002 , H01L2924/00
摘要： First and second semiconductor regions are formed apart from each other on a semiconductor body. A stacked gate is formed on the semiconductor body between the first and second semiconductor regions. The stacked gate has a first side surface, a second side surface opposed to the first side surface, and an upper surface. A contact material is buried in an interlayer insulating film above the semiconductor body, to be adjacent to the first side surface of the stacked gate. The contact material contacts the first semiconductor region. A first insulating film is formed on the second side surface and the upper surface, except the first side surface of the stacked gate adjacent to the contact material. A second insulating film is formed on the first side surface of the stacked gate adjacent to the contact material, and the first insulating film.

15. 发明申请

US20060157801A1 Nonvolatile semiconductor memory device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20060157801A1
公开(公告)日：2006-07-20
申请号：US11302203
申请日：2005-12-14
申请人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
发明人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11543 , Y10S257/909
摘要： A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.
摘要翻译：一种非易失性半导体存储器件的制造方法，具有在存储单元部分的外围电路部分和第二栅电极上形成第一栅电极的步骤，将杂质引入外围电路部分和存储单元部分的步骤，在至少所述存储单元部分之上形成第一绝缘膜的步骤，以及对其中引入了所述杂质的所述半导体衬底进行退火的步骤。第一栅电极具有第一栅极长度。第二栅电极具有比第一栅极长度短的第二栅极长度。

16. 发明申请

US20060120130A1 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield 有权
标题翻译：半导体存储器件能够实现具有高操作可靠性和高产量的芯片
公开(公告)号：US20060120130A1
公开(公告)日：2006-06-08
申请号：US11330352
申请日：2006-01-12
申请人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
发明人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C16/0483 , G11C16/08 , G11C2029/0403 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.
摘要翻译：提供了能够防止由于降低存储单元阵列的端部区域中的蚀刻精度而导致的缺陷的半导体存储器件。第一块由具有存储单元的第一存储单元单元构成，第二块由具有多个存储单元的第二存储单元单元构成，并且存储单元阵列通过将第一块布置在两端部并且将第二块布置在其另一部分上。存储单元阵列的端侧上的第一存储单元单元的结构与第二存储单元单元的结构不同。用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。

17. 发明授权

US07049850B2 Semiconductor device with a voltage detecting device to prevent shoot-through phenomenon in first and second complementary switching devices 有权
标题翻译：具有电压检测装置的半导体装置，用于防止第一和第二互补开关装置中的直通现象
公开(公告)号：US07049850B2
公开(公告)日：2006-05-23
申请号：US10780735
申请日：2004-02-19
申请人： Kazuhiro Shimizu
发明人： Kazuhiro Shimizu
IPC分类号： H03K19/91
CPC分类号： H03K17/063 , H01L27/088
摘要： An HNMOS transistor (4) has its drain electrode connected to the gate electrode of an NMOS transistor (21), and a logic circuit voltage (VCC) is applied to the drain electrode of the NMOS transistor (21) through a resistor (32). A ground potential is applied to the source electrode of the NMOS transistor (21). A drain potential (V2) at the NMOS transistor (21) is monitored by an interface circuit (1), for indirectly monitoring a potential (VS). Thus provided is a high voltage integrated circuit for preventing damage to a semiconductor device used for performing bridge rectification of a power line.
摘要翻译： HNMOS晶体管（4）的漏电极连接到NMOS晶体管（21）的栅电极，并且逻辑电路电压（VCC）通过电阻器（32）施加到NMOS晶体管（21）的漏电极，。接地电位施加到NMOS晶体管（21）的源电极。在NMOS晶体管（21）处的漏极电位（V 2）由接口电路（1）监视，用于间接监视电位（VS）。因此，提供了用于防止对用于执行电力线的桥式整流的半导体装置的损坏的高压集成电路。

18. 发明申请

US20060097309A1 Non-volatile semiconductor memory device having memory cell array suitable for high density and high integration 失效
公开(公告)号：US20060097309A1
公开(公告)日：2006-05-11
申请号：US11305216
申请日：2005-12-19
申请人： Kazuhiro Shimizu , Fumitaka Arai
发明人： Kazuhiro Shimizu , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L29/42324 , H01L2924/0002 , H01L2924/00
摘要： First and second semiconductor regions are formed apart from each other on a semiconductor body. A stacked gate is formed on the semiconductor body between the first and second semiconductor regions. The stacked gate has a first side surface, a second side surface opposed to the first side surface, and an upper surface. A contact material is buried in an interlayer insulating film above the semiconductor body, to be adjacent to the first side surface of the stacked gate. The contact material contacts the first semiconductor region. A first insulating film is formed on the second side surface and the upper surface, except the first side surface of the stacked gate adjacent to the contact material. A second insulating film is formed on the first side surface of the stacked gate adjacent to the contact material, and the first insulating film.

19. 发明授权

US06974979B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US06974979B2
公开(公告)日：2005-12-13
申请号：US10303818
申请日：2002-11-26
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/73 , H01L27/103
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has a plurality of contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.
摘要翻译：选择栅极晶体管具有由第一级导电层和第二级导电层构成的选择栅电极。第一级导电层具有多个接触区域。第二级导电层的部分被去除，位于接触区域上方。在列方向上彼此相邻的两个相邻的选择栅电极被布置成使得一个选择栅电极的接触区域不与另一个选择栅电极的接触区域相对。一个选择栅电极在其与另一个选择栅电极的接触区域相对的部分中移除其第一和第二级导电层。

20. 发明授权

US06943074B2 Nonvolatile semiconductor memory device having a two-layer gate structure and method for manufacturing the same 失效
标题翻译：具有双层栅极结构的非易失性半导体存储器件及其制造方法
公开(公告)号：US06943074B2
公开(公告)日：2005-09-13
申请号：US10412365
申请日：2003-04-14
申请人： Eiji Kamiya , Kazuhiro Shimizu
发明人： Eiji Kamiya , Kazuhiro Shimizu
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L21/8238 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： In a memory cell, a gate oxide film is formed on a surface of semiconductor substrate and a first floating gate is formed on the gate oxide film. An insulating film is formed on a first floating gate and a second floating gate is formed on the insulating film. The first and second floating gates constitute a floating gate in the memory cell. An insulating film between the first floating gate and the second floating gate acts as an etching stopper when a polysilicon constituting the second floating gate is etched.
摘要翻译：在存储单元中，在半导体衬底的表面上形成栅极氧化膜，在栅氧化膜上形成第一浮栅。在第一浮栅上形成绝缘膜，在绝缘膜上形成第二浮栅。第一和第二浮动栅极构成存储单元中的浮动栅极。当构成第二浮栅的多晶硅被蚀刻时，第一浮栅和第二浮栅之间的绝缘膜用作蚀刻阻挡层。

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