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11. 发明申请

US20090127653A1 PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：相变随机访问存储器件及其制造方法
公开(公告)号：US20090127653A1
公开(公告)日：2009-05-21
申请号：US12146179
申请日：2008-06-25
申请人： Cheol Hwi RYU , Hyung Soon PARK , Jong Han SHIN , Jum Yong PARK , Sung Jun KIM
发明人： Cheol Hwi RYU , Hyung Soon PARK , Jong Han SHIN , Jum Yong PARK , Sung Jun KIM
IPC分类号： H01L27/04 , H01L21/20
CPC分类号： H01L27/101 , H01L45/06 , H01L45/124 , H01L45/1683
摘要： A method of manufacturing a phase-change random access memory device includes forming an interlayer insulating film on a semiconductor substrate, on which a bottom structure is formed, and patterning the interlayer insulating film to form a contact hole, forming a spacer on the side wall of the contact hole; forming a dielectric layer in the contact hole, and removing the spacer to form a bottom electrode contact hole. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.
摘要翻译：一种制造相变随机存取存储器件的方法包括在半导体衬底上形成层间绝缘膜，在其上形成底部结构，并对该层间绝缘膜进行构图以形成接触孔，在侧壁上形成间隔物的接触孔; 在接触孔中形成电介质层，并且去除间隔物以形成底部电极接触孔。因此，可以使底部电极接触和相变材料层之间的接触面积最小化。

12. 发明申请

US20080102626A1 METHOD OF FORMING COPPER WIRING IN SEMICONDUCTOR DEVICE 审中-公开
标题翻译：在半导体器件中形成铜线的方法
公开(公告)号：US20080102626A1
公开(公告)日：2008-05-01
申请号：US11776066
申请日：2007-07-11
申请人： Cheol Hwi RYU , Hyung Soon PARK , Jong Han SHIN , Jum Yong PARK , Sung Jun KIM
发明人： Cheol Hwi RYU , Hyung Soon PARK , Jong Han SHIN , Jum Yong PARK , Sung Jun KIM
IPC分类号： H01L21/4763
CPC分类号： H01L21/32125
摘要： A semiconductor package includes method of forming a copper wiring may comprise forming an interlayer insulation film provided with a damascene pattern for wiring over a semiconductor substrate; depositing a barrier metal film over a surface of the damascene pattern and the interlayer insulation film; depositing a copper film over the barrier metal film so as to fill the damascene pattern; and performing an electrochemical mechanical polishing by using a fixed-abrasive pad, supplying an electrolyte solution, and applying an electric field so as to expose the interlayer insulation film.
摘要翻译：半导体封装包括形成铜布线的方法可以包括形成具有用于在半导体衬底上布线的镶嵌图案的层间绝缘膜; 在所述镶嵌图案和所述层间绝缘膜的表面上沉积阻挡金属膜; 在阻挡金属膜上沉积铜膜以填充镶嵌图案; 并通过使用固定研磨垫，供应电解质溶液和施加电场来进行电化学机械抛光，以暴露层间绝缘膜。

13. 发明授权

US07045450B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07045450B2
公开(公告)日：2006-05-16
申请号：US10875052
申请日：2004-06-22
申请人： Sang Ick Lee , Jong Han Shin , Hyung Soon Park
发明人： Sang Ick Lee , Jong Han Shin , Hyung Soon Park
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/7684 , H01L27/10855 , H01L27/10873 , H01L27/10888
摘要： Disclosed is a method of manufacturing a semiconductor device. The method includes the steps of forming gates on a substrate, forming junction areas on a surface of the substrate, forming a first BPSG layer on a resultant structure of the substrate, performing a first CVD process for the first BPSG layer, forming a second BPSG layer on the first BPSG layer, forming a landing plug contact, depositing a polysilicon layer on a resultant structure of the substrate, and performing a second CMP process for the polysilicon layer, the second BPSG layer and the nitride hard mask. The CMP processes are carried by using acid slurry having a high polishing selectivity with respect to the nitride layer, so a step difference between the cell region and the peripheral region is removed, thereby simplifying the semiconductor manufacturing process and removing a dishing phenomenon.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：在衬底上形成栅极，在衬底的表面上形成接合区域，在衬底的所得结构上形成第一BPSG层，对第一BPSG层执行第一CVD工艺，形成第二BPSG 在第一BPSG层上形成着色插头接触，在所得衬底的所得结构上沉积多晶硅层，以及对多晶硅层，第二BPSG层和氮化物硬掩模执行第二CMP工艺。通过使用相对于氮化物层具有高抛光选择性的酸性浆料来进行CMP处理，从而消除了单元区域和外围区域之间的阶跃差异，从而简化了半导体制造工艺并消除了凹陷现象。

14. 发明授权

US5633989A Artificial neural circuit using pulse coding 失效
标题翻译：人工神经电路采用脉冲编码
公开(公告)号：US5633989A
公开(公告)日：1997-05-27
申请号：US298286
申请日：1994-08-31
申请人： Jong-Han Shin , Jong-Geon Shin
发明人： Jong-Han Shin , Jong-Geon Shin
IPC分类号： G06G7/60 , G06F15/18 , G06N3/06 , G06N3/063
CPC分类号： G06N3/0635
摘要： Disclosed is an artificial neural circuit using a pulse coding such as a stochastic pulse coding or a noise feedback pulse coding, the circuit comprising a synapse circuit section for producing and absorbing a current signal proportional to a weight voltage signal upon an externally applied current signal being supplied; a neuron body circuit section for spacio-temporally integrating output signal of the synapse circuit section to produce an analog voltage signal; and an axon hillock circuit for converting the analog voltage signal into a pulse train using a predetermined reference signal. The synapse circuit section including a first input terminal for receiving a first reference voltage; a second input terminal for receiving a second reference voltage; a third input terminal for receiving a third reference voltage; a fourth terminal for receiving the weight voltage signal; a first transistor having drain and source connected to the first reference voltage and a junction point, respectively, and gate connected to the fourth input terminal; a second transistor having drain and source connected to the junction point and the second input terminal, respectively, and gate connected to the third input terminal; and a third transistor having drain and source connected respectively to the junction point and an output terminal of the synapse circuit section, and gate connected to an input terminal for receiving the externally applied current signal.
摘要翻译：公开了使用诸如随机脉冲编码或噪声反馈脉冲编码的脉冲编码的人造神经电路，该电路包括突触电路部分，用于在外部施加的电流信号时产生和吸收与重量电压信号成比例的电流信号供应; 用于对突触电路部分的输出信号进行时空积分以产生模拟电压信号的神经元体电路部分; 以及用于使用预定参考信号将模拟电压信号转换成脉冲串的轴突小丘电路。所述突触电路部分包括用于接收第一参考电压的第一输入端; 用于接收第二参考电压的第二输入端; 用于接收第三参考电压的第三输入端; 用于接收重量电压信号的第四端子; 第一晶体管，其漏极和源极分别连接到第一参考电压和接合点，栅极连接到第四输入端; 第二晶体管，其漏极和源极分别连接到所述连接点和所述第二输入端子，并且栅极连接到所述第三输入端子; 以及第三晶体管，其漏极和源极分别连接到所述连接点和所述突触电路部分的输出端子，并且栅极连接到用于接收外部施加的电流信号的输入端子。

15. 发明授权

US08598012B2 Method for fabricating semiconductor device with buried gates 有权
标题翻译：制造具有埋栅的半导体器件的方法
公开(公告)号：US08598012B2
公开(公告)日：2013-12-03
申请号：US12832137
申请日：2010-07-08
申请人： Jong-Han Shin , Noh-Jung Kwak , Myung-Ok Kim
发明人： Jong-Han Shin , Noh-Jung Kwak , Myung-Ok Kim
IPC分类号： H01L21/76 , H01L21/3205
CPC分类号： H01L21/76229 , H01L21/76897 , H01L27/10876 , H01L27/10894 , H01L29/4236 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes sequentially stacking a pad oxide layer and a hard mask layer over a substrate, forming a device isolation layer over the substrate, forming a capping layer pattern configured to open a first region of the substrate and cover a second region of the substrate, removing the hard mask layer, removing the capping layer pattern, and removing the pad oxide layer.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上顺序堆叠衬垫氧化物层和硬掩模层，在衬底上形成器件隔离层，形成覆盖衬底图案，其构造成打开衬底的第一区域并覆盖第二区域，去除硬掩模层，去除覆盖层图案，以及去除焊盘氧化物层。

16. 发明授权

US08357600B2 Method for fabricating buried gate using pre landing plugs 有权
标题翻译：使用预先着陆插头制造埋栅的方法
公开(公告)号：US08357600B2
公开(公告)日：2013-01-22
申请号：US12613708
申请日：2009-11-06
申请人： Jong-Han Shin , Jum-Yong Park
发明人： Jong-Han Shin , Jum-Yong Park
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/8242
CPC分类号： H01L21/28017 , H01L27/105 , H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L29/4236
摘要： A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer.
摘要翻译：提供一种制造半导体器件的方法，该方法包括在衬底的整个表面上形成插头导电层，蚀刻插头导电层以形成着陆塞，蚀刻层压塞之间的衬底以形成沟槽，形成栅极绝缘层，并且形成在门绝缘层上部分地填充沟槽的掩埋栅极。

17. 发明申请

US20120280313A1 SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：具有开口门的半导体器件及其制造方法
公开(公告)号：US20120280313A1
公开(公告)日：2012-11-08
申请号：US13553307
申请日：2012-07-19
申请人： Jong-Han SHIN , Jum-Yong PARK
发明人： Jong-Han SHIN , Jum-Yong PARK
IPC分类号： H01L29/78
CPC分类号： H01L27/10876 , H01L27/10855 , H01L27/10888 , H01L29/4236
摘要： A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上形成覆盖层，通过在层间塞之间蚀刻衬底形成沟槽，形成掩埋栅极以部分填充沟槽，形成间隙填充层以间隙填充上侧，形成所述着陆塞的突出部分，以及修剪所述着陆塞的突出部分。

18. 发明授权

US08247324B2 Semiconductor device with buried gate and method for fabricating the same 有权
标题翻译：具有埋栅的半导体器件及其制造方法
公开(公告)号：US08247324B2
公开(公告)日：2012-08-21
申请号：US12827385
申请日：2010-06-30
申请人： Jong-Han Shin , Jum-Yong Park
发明人： Jong-Han Shin , Jum-Yong Park
IPC分类号： H01L21/44
CPC分类号： H01L27/10876 , H01L27/10855 , H01L27/10888 , H01L29/4236
摘要： A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上形成覆盖层，通过在层间塞之间蚀刻衬底形成沟槽，形成掩埋栅极以部分填充沟槽，形成间隙填充层以间隙填充上侧，形成所述着陆塞的突出部分，以及修剪所述着陆塞的突出部分。

19. 发明申请

US20120153383A1 SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：具有开口门的半导体器件及其制造方法
公开(公告)号：US20120153383A1
公开(公告)日：2012-06-21
申请号：US13028556
申请日：2011-02-16
申请人： Jong-Han Shin , Bo-Min Park
发明人： Jong-Han Shin , Bo-Min Park
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/76879 , H01L21/28008 , H01L21/76816 , H01L27/10855 , H01L27/10876 , H01L27/10894
摘要： A semiconductor device includes buried gates formed over a substrate, storage node contact plugs which are formed over the substrate and include a pillar pattern and a line pattern disposed over the pillar pattern, and a bit line structure which is formed over the substrate and isolates adjacent ones of the storage node contact plugs from each other.
摘要翻译：半导体器件包括形成在衬底上的掩埋栅极，存储节点接触插塞，其形成在衬底上并且包括柱状图案和设置在柱状图案上的线图案;以及位线结构，其形成在衬底上并隔离相邻存储节点的接点彼此插头。

20. 发明申请

US20120153363A1 SEMICONDUCTOR DEVICE WITH BURIED GATES AND FABRICATION METHOD THEREOF 有权
标题翻译：具有孔栅的半导体器件及其制造方法
公开(公告)号：US20120153363A1
公开(公告)日：2012-06-21
申请号：US13325552
申请日：2011-12-14
申请人： Jong-Han SHIN
发明人： Jong-Han SHIN
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/4236 , H01L27/1052 , H01L27/10873 , H01L27/10876 , H01L27/10888 , H01L27/10894 , H01L29/42352 , H01L29/42356
摘要： A semiconductor device includes a substrate having a cell region and a peripheral region, a buried gate formed over the substrate of the cell region, a peripheral gate formed over the substrate of the peripheral region and comprising a conductive layer, an inter-layer dielectric layer that covers the substrate, and a peripheral bit line formed inside the inter-layer dielectric layer and contacting the conductive layer.
摘要翻译：半导体器件包括具有单元区域和外围区域的衬底，形成在单元区域的衬底上的掩埋栅极，形成在周边区域的衬底上的外围栅极，并且包括导电层，层间电介质层覆盖衬底以及形成在层间电介质层内部并与导电层接触的外围位线。

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