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11. 发明授权

US06909147B2 Multi-height FinFETS 有权
标题翻译：多高度FinFETS
公开(公告)号：US06909147B2
公开(公告)日：2005-06-21
申请号：US10249738
申请日：2003-05-05
申请人： Ingo Aller , Joachim Keinert , Thomas Ludwig , Edward J. Nowak , BethAnn Rainey
发明人： Ingo Aller , Joachim Keinert , Thomas Ludwig , Edward J. Nowak , BethAnn Rainey
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/04 , H01L29/786 , H01L21/8238 , H01L29/78
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/66795
摘要： The present invention provides a FinFET device that has a first fin and a second fin. Each fin has a channel region and source and drain regions that extend from the channel region. The fins have different heights. The invention has a gate conductor positioned adjacent the fins. The gate conductor runs perpendicular to the fins and crosses the channel region of each of the first fin and second fin. The fins are parallel to one another. The ratio of the height of the first fin to the height of the second fin comprises a ratio of one to 2/3. The ratio is used to tune the performance of the transistor and determines the total channel width of the transistor.
摘要翻译：本发明提供一种具有第一鳍片和第二鳍片的FinFET器件。每个散热片具有从沟道区延伸的沟道区和源极和漏极区。翅片具有不同的高度。本发明具有邻近散热片定位的栅极导体。栅极导体垂直于翅片延伸并与第一鳍片和第二鳍片中的每一个的沟道区域交叉。翅片彼此平行。第一翅片的高度与第二翅片的高度的比率为1/2/3的比例。该比率用于调整晶体管的性能并确定晶体管的总通道宽度。

12. 发明授权

US08972758B2 Charge recycling between power domains of integrated circuits 有权
标题翻译：集成电路电源域之间的充电回收
公开(公告)号：US08972758B2
公开(公告)日：2015-03-03
申请号：US13307915
申请日：2011-11-30
申请人： Harry Barowski , Joachim Keinert , Antje Mueller , Tim Niggemeier
发明人： Harry Barowski , Joachim Keinert , Antje Mueller , Tim Niggemeier
IPC分类号： G06F1/32 , G06F1/00
CPC分类号： G06F1/3234 , G06F1/3287 , Y02D10/171 , Y10T307/76
摘要： A mechanism is provided for efficiently recycling a charge from a power domain that is discharging. A side of a discharging power domain normally coupled to a voltage supply is disconnected from the voltage supply. The side of the precharging power domain normally coupled to the voltage supply is currently disconnected from the voltage supply. The side of the discharging power domain normally coupled to the voltage supply is connected to a side of the precharging power domain normally coupled to the voltage supply. A side of the discharging power domain normally coupled to the ground is disconnected from ground. The side of the discharging power domain normally coupled to ground is connected to the voltage supply, thereby precharging the precharging power domain with the charge from the discharging power domain that would normally he lost due to leakage.
摘要翻译：提供了一种用于从放电的动力区域有效地再循环电荷的机构。通常耦合到电压源的放电电源域的一侧与电压源断开。通常耦合到电压源的预充电功率域的一侧当前与电压源断开。通常耦合到电压源的放电功率域的一侧连接到通常耦合到电压源的预充电功率域的一侧。通常耦合到地面的放电电源域的一侧与地面断开。通常耦合到地的放电电源域的一侧连接到电压源，从而由通常由于泄漏而损失的放电电源域的电荷预充电预充电功率域。

13. 发明授权

US08463571B2 Performing reliability analysis of signal wires 失效
标题翻译：执行信号线的可靠性分析
公开(公告)号：US08463571B2
公开(公告)日：2013-06-11
申请号：US12944892
申请日：2010-11-12
申请人： Soroush Abbaspour , Ayesha Akhter , Peter Feldmann , Joachim Keinert
发明人： Soroush Abbaspour , Ayesha Akhter , Peter Feldmann , Joachim Keinert
IPC分类号： G06F19/00 , G01R19/00
CPC分类号： G06F17/5036
摘要： A computer-implemented system, method, and storage device simulate a periodic voltage waveform in a network model of the integrated circuit design. The method then determines resultant current values in each segment of nets of the integrated circuit design resulting from the periodic voltage waveform and performs a Fourier transform of the periodic voltage waveform to generate a frequency domain representation of the periodic voltage waveform. The frequency domain representation comprises multiple Fourier terms, each of the Fourier terms is a frequency that is a multiple of the base frequency. Next, the method performs an AC analysis of the resultant voltage at each frequency of the multiple Fourier terms. The AC analysis provides an electrical current value for each of the frequencies of the Fourier terms for each of the nets. This allows the method to compute a root mean square current through each of the nets based on the AC analysis. Then, the method determines whether the root mean square current for any of the segments of the nets exceeds a current limit, and reports any segment of the nets for which the root mean square current exceeds the current limit.
摘要翻译：计算机实现的系统，方法和存储设备模拟集成电路设计的网络模型中的周期性电压波形。然后，该方法确定由周期性电压波形产生的集成电路设计的网络的每个段中的合成电流值，并执行周期性电压波形的傅立叶变换以产生周期性电压波形的频域表示。频域表示包括多个傅立叶项，每个傅立叶项是基频的倍数的频率。接下来，该方法对多傅里叶项的每个频率进行所得到的电压的AC分析。 AC分析为每个网络的傅立叶项的每个频率提供电流值。这允许该方法基于AC分析来计算通过每个网络的均方根电流。然后，该方法确定网络的任何段的均方根电流是否超过电流限制，并且报告均方根电流超过电流极限的网络的任何段。

14. 发明授权

US08418110B2 Using port obscurity factors to improve routing 失效
标题翻译：使用端口隐蔽因素来改善路由
公开(公告)号：US08418110B2
公开(公告)日：2013-04-09
申请号：US12875081
申请日：2010-09-02
申请人： Joachim Keinert , Thomas Ludwig
发明人： Joachim Keinert , Thomas Ludwig
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： An integrated circuit characterized by a netlist may be routed using a routing priority list that may be created using port obscurity factors. A port obscurity factor may indicate how difficult it may be to route to that port and may be calculated as being inversely proportional to the number of routing tracks that may be connectable to that port. Routing priorities for the nets of the netlist may then be created using the port obscurity factors of the ports in the net. Routing may then be done in the order determined by the routing priority list and the generated layout information stored in a computer useable medium. In some cases, routing may be performed using multiple routing passes where a new routing priority list may be calculated for each routing pass.
摘要翻译：以网表为特征的集成电路可以使用可以使用端口遮蔽因素创建的路由优先级列表进行路由。端口遮蔽因素可以指示路由到该端口是多么困难，并且可以被计算为与可以连接到该端口的路由轨道的数量成反比。可以使用网络端口的端口隐含因素来创建网表的网络优先级。然后可以按路由优先级列表确定的顺序和存储在计算机可用介质中的生成的布局信息来完成路由。在某些情况下，路由可以使用多个路由遍历来执行，其中可以针对每个路由选路来计算新的路由优先级列表。

15. 发明申请

US20130074025A1 POST TIMING LAYOUT MODIFICATION FOR PERFORMANCE 失效
标题翻译：启动时序布局修改性能
公开(公告)号：US20130074025A1
公开(公告)日：2013-03-21
申请号：US13236977
申请日：2011-09-20
申请人： Uwe Fassnacht , Veit Gernhoefer , Michael S. Gray , Joachim Keinert
发明人： Uwe Fassnacht , Veit Gernhoefer , Michael S. Gray , Joachim Keinert
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/84
摘要： A mechanism is provided for post timing layout modification for performance. The mechanism selectively applies layout modification based on timing analysis at the path level. The mechanism applies stress only to transistors that are in a setup critical path without applying stress to transistors in hold critical paths. The mechanism may use a method to apply stress to improve performance of a transistor in a setup critical path, as long as the stress does not also improve performance of a neighboring transistor in a hold critical path. In some instances, the mechanism may apply stress to improve performance of a transistor in a setup critical path while simultaneously degrading performance of a transistor in a hold critical path.
摘要翻译：提供了一种用于性能的后期时序布局修改的机制。该机制基于路径级别的时序分析，选择性地应用布局修改。该机制仅将压力应用于处于设置关键路径的晶体管，而不对保持关键路径中的晶体管施加压力。该机制可以使用施加应力以提高晶体管在设置关键路径中的性能的方法，只要该应力不会改善保持关键路径中的相邻晶体管的性能即可。在一些情况下，该机制可以施加应力以改善设置关键路径中的晶体管的性能，同时降低保持关键路径中的晶体管的性能。

16. 发明授权

US07962877B2 Port assignment in hierarchical designs by abstracting macro logic 有权
标题翻译：通过抽象宏逻辑在分层设计中的端口分配
公开(公告)号：US07962877B2
公开(公告)日：2011-06-14
申请号：US12185943
申请日：2008-08-05
申请人： Joachim Keinert , Juergen Koehl , Thomas Ludwig
发明人： Joachim Keinert , Juergen Koehl , Thomas Ludwig
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/84
摘要： A method to reduce the problem complexity maintains a relatively high quality port assignment by abstracting local connections in the macro when performing the port assignment. This is done for netlength, congestion as well as timing. The internal netlist of the macro is abstracted in such a way that the optimization of the external interconnect can be done in an efficient manner. Three levels of abstractions are described. A first level optimizes the top level interconnect, a second level optimizes the top level and macro interconnects, while a third level optimizes the top level timing.
摘要翻译：当执行端口分配时，减少问题复杂度的方法通过抽象宏中的本地连接来维持相对较高质量的端口分配。这是为了网络长度，拥塞以及时序而完成的。宏的内部网表被抽象出来，可以以有效的方式完成外部互连的优化。描述了三个层次的抽象。第一级优化顶级互连，第二级优化顶级和宏互连，而第三级优化顶级时间。

17. 发明申请

US20110072407A1 Automatic Positioning of Gate Array Circuits in an Integrated Circuit Design 有权
标题翻译：门阵列电路在集成电路设计中的自动定位
公开(公告)号：US20110072407A1
公开(公告)日：2011-03-24
申请号：US12563021
申请日：2009-09-18
申请人： Joachim Keinert , Douglass T. Lamb , David W. Lewis , Shyam Ramji
发明人： Joachim Keinert , Douglass T. Lamb , David W. Lewis , Shyam Ramji
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An automated method and apparatus for positioning gate array circuits in an integrated circuit design. An initial integrated circuit design includes logic cells and gate array fill circuits positioned thereon. The gate array fill circuits are positioned in available space between the adjacent logic cells so as to fill the available space with the maximum gate array fill circuits. A gate array logic element to be positioned in the integrated circuit design, such as may be required by an engineering change to the circuit design, is automatically positioned between adjacent logic cells so as to allow for full utilization of any space remaining between the adjacent logic cells by gate array fill circuits.
摘要翻译：一种用于在集成电路设计中定位门阵列电路的自动化方法和装置。初始集成电路设计包括位于其上的逻辑单元和门阵列填充电路。门阵列填充电路位于相邻逻辑单元之间的可用空间中，以便用最大门阵列填充电路填充可用空间。位于集成电路设计中的门阵列逻辑元件（例如可能需要通过电路设计的工程改变）被自动地定位在相邻逻辑单元之间，以便允许充分利用相邻逻辑之间剩余的任何空间电池通过门阵列填充电路。

18. 发明授权

US06237128B1 Method and apparatus for enabling parallel layout checking of designing VLSI-chips 失效
标题翻译：用于设计VLSI芯片的并行布局检查的方法和装置
公开(公告)号：US06237128B1
公开(公告)日：2001-05-22
申请号：US08944797
申请日：1997-10-06
申请人： Harald Folberth , Joachim Keinert , Jürgen Koehl , Kurt Pollmann , Oliver Rettig
发明人： Harald Folberth , Joachim Keinert , Jürgen Koehl , Kurt Pollmann , Oliver Rettig
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： The present invention pertains to a design method for VLSI-chips. The chips are partitioned into segments in order to enable DRC and LVS. Thus, the memory requirements are kept below the limits of the platform used for the verification and the turnaround time is drastically reduced.
摘要翻译：本发明涉及VLSI芯片的设计方法。这些芯片被划分成段，以便能够实现DRC和LVS。因此，存储器要求保持低于用于验证的平台的限制，并且周转时间大大减少。

19. 发明授权

US4614885A Phase splitter with latch 失效
标题翻译：相分离器带闩锁
公开(公告)号：US4614885A
公开(公告)日：1986-09-30
申请号：US630544
申请日：1984-07-13
申请人： Rudolf Brosch , Joachim Keinert , Erich Klink , Friedrich C. Wernicke
发明人： Rudolf Brosch , Joachim Keinert , Erich Klink , Friedrich C. Wernicke
IPC分类号： H03K3/286 , H03K3/288 , H03K5/02 , H03K5/151 , H03K3/023
CPC分类号： H03K3/288
摘要： A phase splitter with latch comprises a true complement generator in the form of a current switch (T1, T2, T3, R3) which supplies two complementary output signals in response to an input signal (VIN). The outputs of this true complement generator are in each case connected to an associated emitter follower (T4, T5). The two emitter followers (T4, T5) have identical emitter resistors (R6, R7) which simultaneously serve as collector load resistors of two cross-coupled transistors (T6, T7) also comprise identical but higher emitter resistors (R13, R14) than the emitter followers (T6, T7). The emitters of the cross-coupled transistors (T6, T7) are each connected to one of the two inputs of an output stage (T8, T9, T11) consisting of a current switch. This current switch is connected to operating voltage (VEE) through a clock-controlled transistor (T11). Upon actuation of the output stage, i.e., when transistor (T11) is on, the active emitter resistance of one of the cross-coupled transistors (T6, T7) is pulled below the value of the emitter resistors (R6, R7) of the emitter followers (T4, T5), thus causing the latch circuit to be latched as a function of the input signal.
摘要翻译：具有锁存器的分相器包括形式为电流开关（T1，T2，T3，R3）形式的真互补发生器，其根据输入信号（VIN）提供两个互补输出信号。这种真互补发生器的输出在每种情况下都连接到相关的射极跟随器（T4，T5）。两个发射极跟随器（T4，T5）具有相同的发射极电阻（R6，R7），其同时用作两个交叉耦合晶体管（T6，T7）的集电极负载电阻，其也包括相同但较高的发射极电阻（R13，R14）发射极跟随器（T6，T7）。交叉耦合晶体管（T6，T7）的发射极各自连接到由电流开关组成的输出级（T8，T9，T11）的两个输入之一。该电流开关通过时钟控制的过渡器（T11）连接到工作电压（VEE）。在激励输出级时，即当晶体管（T11）导通时，其中一个交叉耦合晶体管（T6，T7）的有源发射极电阻被拉低到低于发射极电阻（R6，R7）的值发射极跟随器（T4，T5），从而使闩锁电路根据输入信号被锁存。

20. 发明授权

US08495547B2 Providing secondary power pins in integrated circuit design 有权
标题翻译：在集成电路设计中提供二次电源引脚
公开(公告)号：US08495547B2
公开(公告)日：2013-07-23
申请号：US12910336
申请日：2010-10-22
申请人： Joachim Keinert , Douglass T. Lamb , Peter J. Osler
发明人： Joachim Keinert , Douglass T. Lamb , Peter J. Osler
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： An integrated circuit (IC) design with multiple metal layers containing cells requiring secondary power supply. After placing the cells and stripes of a primary power/ground grid in metal layers of the IC design, specific cells are provided with secondary power stripes in a first metal layer. The secondary power stripes are designed in such a way that each secondary power/ground stripe exhibits a full overlap with a stripe of a corresponding primary power/ground grid in a different metal layer. Subsequently, signals from the IC design are routed, and power vias between the primary power/ground grid stripes and the secondary power/ground stripes are generated.
摘要翻译：集成电路（IC）设计，具有多个含有需要二次电源的电池的金属层。在将主电源/接地网格的电池和条纹放置在IC设计的金属层中之后，特定电池在第一金属层中设置有次级电源条。次级功率条纹被设计成使得每个次级电源/接地条带与不同金属层中的对应的主电源/接地网格的条带完全重叠。随后，来自IC设计的信号被路由，并且产生主电源/接地网格条和次级电源/接地条之间的电源通孔。

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