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11. 发明申请

US20080018872A1 METHOD AND APPARATUS FOR MANUFACTURING DIAMOND SHAPED CHIPS 有权
标题翻译：用于制造金刚石型材的方法和装置
公开(公告)号：US20080018872A1
公开(公告)日：2008-01-24
申请号：US11865728
申请日：2007-10-01
申请人： Robert Allen , John Cohn , Scott Gould , Peter Habitz , Juergen Koehl , Gustavo Tellez , Ivan Wemple , Paul Zuchowski
发明人： Robert Allen , John Cohn , Scott Gould , Peter Habitz , Juergen Koehl , Gustavo Tellez , Ivan Wemple , Paul Zuchowski
IPC分类号： G03B27/42
CPC分类号： H01L27/0207
摘要： In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.
摘要翻译：在第一方面中，用于对晶片上的芯片进行成像的本发明的装置包括具有多个倾斜侧面的组合金刚石芯片图像和切口图像。组合的金刚石芯片图像和切口图像包括金刚石芯片图像，其包括与金刚石芯片图像的至少一个对角线平行的多个芯片图像行，并且包括与金刚石芯片图像相邻的切痕图像。切口图像包括平行于金刚石切片图像的至少一个对角线的至少一个切痕图像行。该装置还包括从组合的金刚石片图像和切痕图像延伸到步进器的曝光场的至少周边的阻挡材料。在第二方面，成像装置包括n侧多边形组合芯片图像和切口图像。还提供了制造芯片的创造性方法和根据本发明方法制造的晶片。

12. 发明申请

US20070115019A1 METHOD AND APPARATUS FOR STORING CIRCUIT CALIBRATION INFORMATION 失效
标题翻译：存储电路校准信息的方法和装置
公开(公告)号：US20070115019A1
公开(公告)日：2007-05-24
申请号：US11164040
申请日：2005-11-08
申请人： Anthony Bonaccio , Allen Haar , Joseph Iadanza , Douglas Stout , Ivan Wemple
发明人： Anthony Bonaccio , Allen Haar , Joseph Iadanza , Douglas Stout , Ivan Wemple
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R35/005
摘要： A method for altering circuit characteristics to make them independent of processing parameters of devices within an integrated circuit is disclosed. A process parameter is measured by a kerf or on-chip built-in test on a selective set of chip on a wafer, and the results are stored on a storage device within each respective chip. Then, for each of the remaining chips, a two-dimensional interpolation is performed to determine the process parameter value for the respective chip based on the measured value. The interpolated values are recorded along with the coordinates of the chip in an efuse control file. Such information is subsequently stored into an efuse module within the chip. On-chip digital control structures are used to adjust certain operational characteristics of a functional component within the chip based on the information stored in the efuse module.
摘要翻译：公开了一种用于改变电路特性以使它们与集成电路内的器件的处理参数无关的方法。通过在晶片上的选择性芯片组上的切口或片上内置测试来测量工艺参数，并将结果存储在每个相应芯片内的存储装置上。然后，对于剩余的每个芯片，执行二维内插，以基于测量值确定各个芯片的处理参数值。内插值与芯片在efuse控制文件中的坐标一起被记录。这样的信息随后被存储在芯片内的efuse模块中。片上数字控制结构用于根据存储在efuse模块中的信息来调整芯片内的功能组件的某些操作特性。

13. 发明申请

US20050273744A1 IC TILING PATTERN METHOD, IC SO FORMED AND ANALYSIS METHOD 有权
标题翻译： IC TILING PATTERN方法，IC形成和分析方法
公开(公告)号：US20050273744A1
公开(公告)日：2005-12-08
申请号：US11160339
申请日：2005-06-20
申请人： Robert Allen , John Cohn , Peter Habitz , William Leipold , Ivan Wemple , Paul Zuchowski
发明人： Robert Allen , John Cohn , Peter Habitz , William Leipold , Ivan Wemple , Paul Zuchowski
IPC分类号： G06F9/45 , G06F13/00 , G06F17/50 , H01L21/321 , H01L23/48 , H01L23/52 , H01L23/528 , H01L23/535 , H01L27/02
CPC分类号： G06F17/5068 , H01L21/3212 , H01L27/0207
摘要： The invention provides a method for providing an integrated circuit (6) having a substantially uniform density between parts (10, 12, 14 and 16) of the IC that are non-orthogonally angled. In particular, the invention provides fill tiling patterns (32, 34) oriented substantially parallel to electrical structure regardless of their angle. A method of electrical analysis based on this provision is also provided as is a related program product.
摘要翻译：本发明提供一种用于提供集成电路（6）的方法，所述集成电路（6）在IC的非正交角的部分（10,12,14和16）之间具有基本均匀的密度。特别地，本发明提供了基本上平行于电气结构定向的填充平铺图案（32,34），而不管其角度如何。还提供了基于该规定的电分析方法，相关程序产品也是如此。

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