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    • 13. 发明申请
    • ANALOG IN POWER SUPPLY MODULE
    • 模拟电源模块
    • US20130188447A1
    • 2013-07-25
    • US13750415
    • 2013-01-25
    • Inova, Ltd.
    • Zeljko BacanekTimothy D. Hladik
    • G01V1/24
    • G01V1/247
    • The present disclosure relates methods and apparatus conducting a seismic survey. The apparatus includes an analog interface and power supply both disposed in a housing. The analog interface is configured to receive analog seismic data from a seismic sensor. The apparatus includes one or more of: (i) an isolation transformer disposed between the power supply and the analog interface and (ii) a analog interface clock configured to synchronized with a power supply clock. The method may include reducing power transmission losses and/or the effect of power supply noise on the seismic signals.
    • 本公开涉及进行地震勘测的方法和装置。 该装置包括设置在壳体中的模拟接口和电源。 模拟接口被配置为从地震传感器接收模拟地震数据。 该装置包括以下一个或多个:(i)设置在电源和模拟接口之间的隔离变压器和(ii)被配置为与电源时钟同步的模拟接口时钟。 该方法可以包括减少功率传输损耗和/或电源噪声对地震信号的影响。
    • 18. 发明授权
    • High-precision time synchronization for a cabled network in linear topology
    • 线性拓扑中电缆网络的高精度时间同步
    • US09297917B2
    • 2016-03-29
    • US13750264
    • 2013-01-25
    • INOVA, LTD.
    • Wah Hong MahHua AiLin ZhuTimothy D. Hladik
    • G01V1/22G01V1/28G01V1/26
    • G01V1/28G01V1/22G01V1/26G01V2210/12
    • The present disclosure relates to methods and apparatuses for reducing propagation delay uncertainty while conducting a survey. The apparatus includes a plurality of nodes along a communication path configured to allow communication between nodes with only one clock domain boundary crossing. Each node may include a clock, a memory, and a processor. The plurality of nodes is arranged in a linear topology. The linear topology may have first and second nodes on the ends of the line. The method may include reducing propagation delay uncertainty using at least one time marker transmitted to each of the plurality of nodes without crossing a clock domain boundary of any other node.
    • 本公开涉及在进行调查时减少传播延迟不确定性的方法和装置。 该装置包括沿着通信路径的多个节点,其被配置为允许仅具有一个时钟域边界交叉的节点之间的通信。 每个节点可以包括时钟,存储器和处理器。 多个节点被布置成线性拓扑。 线性拓扑结构可以在线路的末端具有第一和第二节点。 该方法可以包括使用至少一个传送到多个节点中的每个节点的时间标记来减少传播延迟不确定性,而不会跨越任何其他节点的时钟域边界。