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11. 发明授权

US5349559A Internal voltage generating circuit 失效
标题翻译：内部电压发生电路
公开(公告)号：US5349559A
公开(公告)日：1994-09-20
申请号：US940205
申请日：1992-08-18
申请人： Yong-Bo Park , Hyung-Kyu Lim
发明人： Yong-Bo Park , Hyung-Kyu Lim
IPC分类号： G05F3/24 , G05F1/46 , G06F1/28 , G11C5/14 , G11C11/401 , G11C11/407 , G11C11/4074 , G11C11/413 , G11C29/00 , G11C29/06 , G11C29/50
CPC分类号： G11C5/147 , G05F1/465 , G06F1/28 , G11C11/4074 , G11C29/50 , G06F2201/81
摘要： A circuit for generating an internal voltage to be supplied to memory elements of a semiconductor memory chip during normal operation and for providing an external voltage to the memory elements during a burn-in test operation. The circuit may be constructed with a driver circuit (50) which receives an external voltage and is controlled to generate the internal voltage. A comparator (300) compares the internal voltage to a first reference voltage to produce a control signal G2 to control the driver circuit (50). An external voltage detector (100) compares a second reference voltage to the external voltage to generate control signal B2. A driver control circuit (200) is enabled by control signal B2, if the external voltage is less than the second reference voltage, to pass control signal G2 to the driver circuit and thereby enable generation of the internal voltage to be equal to, or less than, the operating voltage of the semiconductor memory chip. The driver control circuit is disabled by control signal B2 if the external voltage is greater than the second reference voltage, thereby preventing the control signal G2 of the comparator from controlling conduction by the driver circuit (50) to enable output of the external voltage exhibiting an elevated amplitude to the memory elements for burn-in test operation.
摘要翻译：一种用于在正常操作期间产生要提供给半导体存储器芯片的存储元件的内部电压并且用于在老化测试操作期间向存储器元件提供外部电压的电路。电路可以由接收外部电压的驱动电路（50）构成，并被控制以产生内部电压。比较器（300）将内部电压与第一参考电压进行比较，以产生控制信号G2以控制驱动电路（50）。外部电压检测器（100）将第二参考电压与外部电压进行比较以产生控制信号B2。如果外部电压小于第二参考电压，则通过控制信号B2使驱动器控制电路（200）启动，以将控制信号G2传递给驱动器电路，从而使内部电压的产生等于或等于或更小比半导体存储器芯片的工作电压高。如果外部电压大于第二参考电压，则控制信号B2禁止驱动器控制电路，从而防止比较器的控制信号G2控制驱动电路（50）的导通，以便能够输出外部电压升高幅度到记忆元件进行老化测试操作。

12. 发明授权

US5326999A Non-volatile semiconductor memory device and manufacturing method thereof 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US5326999A
公开(公告)日：1994-07-05
申请号：US976200
申请日：1992-11-13
申请人： Keon-soo Kim , Hyung-kyu Lim
发明人： Keon-soo Kim , Hyung-kyu Lim
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/68 , G11C11/34
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L27/11524
摘要： Disclosed is a non-volatile semiconductor memory device and the manufacturing method thereof. The non-volatile semiconductor memory device comprising a semiconductor substrate, and a group of gates electrically isolated from each other and formed on the semiconductor substrate, wherein the group of gates comprises a floating gate formed with a first conductive layer, a control gate formed with a second conductive layer laminated on the floating gate and select gates formed with the first conductive layer and the second conductive layer/formed on both the opposite side of the floating gate and the control gate and with an interposing impurity diffusion region formed on the semiconductor substrate, and wherein the select gates formed with the first conductive layer and the second conductive layer forms contacts on a field oxidation layer, thereby being connected with each other. The gate of the select transistor is formed as a first conductive layer by a self-aligned etching process and a butted contact process. Meanwhile, prior to forming a tunnel oxidized film, a buried n.sup.- layer is formed on a tunnel region pattern so as to be self-aligned, thereby reducing a distance between the select transistor and the storage transistor to within photolithographic processing limits so as to realize the high-integration of the EEPROM.
摘要翻译：公开了一种非易失性半导体存储器件及其制造方法。所述非易失性半导体存储器件包括半导体衬底和形成在所述半导体衬底上的彼此电隔离的一组栅极，其中所述栅极组包括形成有第一导电层的浮置栅极，形成有层叠在浮置栅极上的第二导电层和形成有第一导电层和第二导电层的选择栅极，形成在浮置栅极和控制栅极的相对侧上，以及形成在半导体衬底上的中间杂质扩散区域并且其中形成有第一导电层和第二导电层的选择栅极在场氧化层上形成接触，从而彼此连接。选择晶体管的栅极通过自对准蚀刻工艺和对接接触工艺形成为第一导电层。同时，在形成隧道氧化膜之前，在隧道区域图案上形成掩埋的n层以进行自对准，从而将选择晶体管和存储晶体管之间的距离减小到光刻处理限度内，从而实现EEPROM的高集成度。

13. 发明授权

US5293350A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5293350A
公开(公告)日：1994-03-08
申请号：US18240
申请日：1993-02-17
申请人： Jin-Ki Kim , Hyung-Kyu Lim
发明人： Jin-Ki Kim , Hyung-Kyu Lim
IPC分类号： G11C17/00 , G11C16/00 , G11C16/02 , G11C16/06 , G11C16/12 , G11C7/00
CPC分类号： G11C16/12
摘要： A nonvolatile semiconductor memory device having a page program mode of operation. The device including a data input buffer for receiving program data from a data line and a plurality of program voltage generating circuits each of which is selectively operable for generating a program voltage output having a first and second logic level. The device further including a plurality of first selecting MOS transistors coupled to respective ones of the program voltage generating circuits and alternating ones of bit lines included in the memory device and a plurality of second selecting MOS transistors coupled to respective ones of the program voltage generating circuits and a second sequences of alternating one of the bit lines. A select circuit having a first output connected to each of the first selecting transistors and a second output connected to each of the second selecting transistors for selectively turning on either of the first and second selecting transistors to thereby selectively couple either the bit lines of the first and second sequence to the program voltage output of the respective ones of the program voltage generating circuits.
摘要翻译：一种具有页面编程操作模式的非易失性半导体存储器件。该装置包括用于从数据线接收节目数据的数据输入缓冲器和多个编程电压产生电路，每个编程电压产生电路可选择地可操作用于产生具有第一和第二逻辑电平的编程电压输出。该装置还包括耦合到各个编程电压产生电路的多个第一选择MOS晶体管和包括在存储器件中的位线的交替位置以及耦合到各个编程电压产生电路的多个第二选择MOS晶体管以及交替一个位线的第二序列。一种选择电路，其具有连接到每个第一选择晶体管的第一输出端和连接到每个第二选择晶体管的第二输出端，用于选择性地导通第一和第二选择晶体管中的任一个，从而选择性地耦合第一选择晶体管的位线以及对各个编程电压产生电路的编程电压输出的第二序列。

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