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    • 15. 发明申请
    • PHASE LOCKED LOOP HAVING CONTINUOUS BANK CALIBRATION UNIT AND METHOD OF PREVENTING UNLOCKING OF PLL
    • 具有连续银行校准单元的相位锁定环和防止PLL解锁的方法
    • US20080088378A1
    • 2008-04-17
    • US11868657
    • 2007-10-08
    • Hyun Ji SONGKyung Lok KIMKyoo Hyun LIM
    • Hyun Ji SONGKyung Lok KIMKyoo Hyun LIM
    • H03L7/099H03L7/08
    • H03L7/099H03L7/10H03L2207/06
    • A phase locked loop (PLL) having a continuous bank calibration unit and a method of preventing unlocking of the PLL are provided. The PLL includes a main circuit, a voltage controlled oscillator (VCO), and a continuous bank calibration unit. The main circuit outputs a control voltage in response to an external clock signal and an oscillating signal. The VCO outputs the oscillating signal in response to the control voltage and the bank calibration signal. The continuous bank calibration unit compares the received control voltage with a window voltage having at least two comparison values to output the bank calibration signal. In the PLL having a continuous bank calibration unit, although the control voltage varies with external factors such as temperature, the bank of the VCO is immediately and suitably calibrated to prevent unlocking of the PLL, so that it is possible to Improve an output characteristic of the VCO.
    • 提供了具有连续存储体校准单元的锁相环(PLL)和防止锁定解锁的方法。 PLL包括主电路,压控振荡器(VCO)和连续存储体校准单元。 主电路响应于外部时钟信号和振荡信号输出控制电压。 VCO响应于控制电压和组校准信号输出振荡信号。 连续存储体校准单元将接收到的控制电压与具有至少两个比较值的窗口电压进行比较,以输出存储体校准信号。 在具有连续组合校准单元的PLL中,尽管控制电压随外部因素如温度而变化,但VCO的存储体立即被适当地校准以防止PLL的解锁,从而可以提高输出特性 VCO。