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11. 发明授权

US06642572B2 Nonvolatile semiconductor memory device and method for fabricating the same 失效
公开(公告)号：US06642572B2
公开(公告)日：2003-11-04
申请号：US10382520
申请日：2003-03-07
申请人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
发明人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

12. 发明授权

US06538275B2 Nonvolatile semiconductor memory device and method for fabricating the same 失效
公开(公告)号：US06538275B2
公开(公告)日：2003-03-25
申请号：US09902942
申请日：2001-07-12
申请人： Nobuyo Sugiyama , Hiromasa Fujimoto , Shinji Odanaka , Seiki Ogura
发明人： Nobuyo Sugiyama , Hiromasa Fujimoto , Shinji Odanaka , Seiki Ogura
IPC分类号： H01L2976
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween. Within the semiconductor substrate and in the vicinity of the stepped portion, there is formed a depletion control layer which is composed of a heavily doped impurity region and formed to extend from a position located under the floating gate electrode and at a distance from the upper corner of the stepped portion toward the lower corner of the stepped portion and adjoin the end portion of a drain region without reaching a step side region.

13. 发明授权

US06337500B1 Semiconductor device and method for fabricating the same 失效
公开(公告)号：US06337500B1
公开(公告)日：2002-01-08
申请号：US09099195
申请日：1998-06-18
申请人： Hiroaki Nakaoka , Hiromasa Fujimoto , Atsushi Hori , Takashi Uehara , Takehiro Hirai
发明人： Hiroaki Nakaoka , Hiromasa Fujimoto , Atsushi Hori , Takashi Uehara , Takehiro Hirai
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L29/66772 , H01L29/78612 , H01L29/78621 , Y10S438/91
摘要： In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions. Thus, it is possible to provide an SOI transistor causing no decrease in the source/drain breakdown voltage resulting from substrate floating effects and causing little OFF leakage current because of the activation of the parasitic transistor.

14. 发明授权

US5227323A Method of manufacturing capacitor elements in an integrated circuit having a compound semiconductor substrate 失效
标题翻译：在具有化合物半导体衬底的集成电路中制造电容器元件的方法
公开(公告)号：US5227323A
公开(公告)日：1993-07-13
申请号：US901296
申请日：1992-06-19
申请人： Mitsuru Nishitsuji , Hiromasa Fujimoto
发明人： Mitsuru Nishitsuji , Hiromasa Fujimoto
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8252 , H01L27/06
CPC分类号： H01L21/8252 , H01L27/0605
摘要： A capacitor element is formed in an integrated circuit having a compound semiconductor substrate such as a GaAs substrate and having Schottky type FETs formed on the substrate, with the capacitor element being formed by a process in which a lower electrode of a capacitor element and a lower layer portion of the gate electrode of a FET are formed by the same processing step from a high melting-point tungsten compound, a film of insulating material having a high dielectric coefficient is formed overall and is patterned to expose the gate electrode lower layer, and a high-conductance metallic film is then deposited overall and patterned to form an upper electrode of the capacitor element and an upper layer portion of the gate electrode. Capacitor elements and FETs can thereby be formed in such an IC by a simple process, while substantial reduction of the substrate area occupied by each capacitor element can be achieved.
摘要翻译：电容器元件形成在具有诸如GaAs衬底的化合物半导体衬底和形成在衬底上的肖特基型FET的集成电路中，电容器元件通过以下工艺形成，其中电容器元件的下电极和下电极通过与高熔点钨化合物相同的处理步骤形成FET的栅电极的层部分，整体形成具有高介电系数的绝缘材料的膜，并对其进行构图以露出栅电极下层，以及然后将高电导金属膜整体沉积并图案化以形成电容器元件的上电极和栅电极的上层部分。因此，可以通过简单的工艺在这种IC中形成电容器元件和FET，同时可以实现每个电容器元件占据的基板面积的显着减小。

15. 发明授权

US08779524B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08779524B2
公开(公告)日：2014-07-15
申请号：US13554386
申请日：2012-07-20
申请人： Yoshiya Moriyama , Hiromasa Fujimoto , Satoru Itou , Susumu Akamatsu , Hiroshi Ohkawa
发明人： Yoshiya Moriyama , Hiromasa Fujimoto , Satoru Itou , Susumu Akamatsu , Hiroshi Ohkawa
IPC分类号： H01L27/092 , H01L29/78 , H01L21/768 , H01L21/28
CPC分类号： H01L29/7843 , H01L21/28123 , H01L21/28176 , H01L21/76895 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L23/485 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first-conductivity-type first MIS transistor and a second-conductivity-type second MIS transistor. The first and second MIS transistors include a first and a second gate insulating film formed on a first and a second active region surrounded by a separation region of a semiconductor substrate, and a first and a second gate electrode formed on the first and second gate insulating films. The first and second gate insulating films are separated from each other on a first separation region of the separation region. A distance s between first ends of the first and second active regions facing each other with the first separation region being interposed therebetween, and a protrusion amount d1 from the first end of the first active region to a first end of the first gate insulating film located on the first separation region establish a relationship d1
摘要翻译：半导体器件包括第一导电型第一MIS晶体管和第二导电型第二MIS晶体管。第一和第二MIS晶体管包括形成在由半导体衬底的分离区围绕的第一和第二有源区上的第一和第二栅极绝缘膜，以及形成在第一和第二栅极绝缘上的第一和第二栅电极电影。第一和第二栅极绝缘膜在分离区域的第一分离区域上彼此分离。在第一和第二有源区域的第一端之间的距离为第一和第二有源区域之间的距离，第一分隔区域彼此相对，并且从第一有源区域的第一端到第一栅极绝缘膜的第一端的突出量d1 在第一分离区域建立关系d1 <0.5s。

16. 发明授权

US08604554B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08604554B2
公开(公告)日：2013-12-10
申请号：US13399102
申请日：2012-02-17
申请人： Satoru Itou , Hiromasa Fujimoto , Susumu Akamatsu , Toshie Kutsunai
发明人： Satoru Itou , Hiromasa Fujimoto , Susumu Akamatsu , Toshie Kutsunai
IPC分类号： H01L21/70
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device includes a first and a second MIS transistor. The first and second MIS transistors include a first and a second gate electrode formed on a first and a second active region with a first and a second gate insulating film being formed therebetween, first and second sidewalls including a first and a second inner sidewall formed on side surfaces of the first and second gate electrodes and having an L-shaped cross-section, and first and second source/drain regions formed in the first and second active regions laterally outside the first and second sidewalls. The first source/drain regions include a silicon compound layer formed in trenches provided in the first active region and causes a first stress in a gate length direction of a channel region in the first active region. A width of the first inner sidewall is smaller than a width of the second inner sidewall.
摘要翻译：半导体器件包括第一和第二MIS晶体管。第一和第二MIS晶体管包括形成在第一和第二有源区上的第一和第二栅电极，其间形成有第一和第二栅极绝缘膜，第一和第二侧壁包括形成在第一和第二内侧壁上的第一和第二内侧壁所述第一和第二栅电极的侧表面具有L形横截面，以及在所述第一和第二有源区中形成在所述第一和第二侧壁的横向外侧的第一和第二源/漏区。第一源极/漏极区域包括形成在设置在第一有源区域中的沟槽中的硅化合物层，并且在第一有源区域中的沟道区域的栅极长度方向上产生第一应力。所述第一内侧壁的宽度小于所述第二内侧壁的宽度。

17. 发明申请

US20090065807A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090065807A1
公开(公告)日：2009-03-12
申请号：US12201407
申请日：2008-08-29
申请人： Hiromasa FUJIMOTO
发明人： Hiromasa FUJIMOTO
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823842 , H01L21/823864 , H01L29/7843
摘要： The semiconductor device includes: a first MIS transistor formed on a first region of a first conductivity type in a semiconductor substrate; and a second MIS transistor formed on a second region of a second conductivity type in the semiconductor substrate. The first MIS transistor has a first gate insulating film and a first gate electrode formed on the first region, first sidewalls formed on the side faces of the first gate electrode, and first source/drain regions made of silicon formed in portions of the first region. The second MIS transistor has a second gate insulating film and a second gate electrode formed on the second region, second sidewalls formed on the side faces of the second gate electrode, and second source/drain regions including silicon germanium formed in portions of the second region. The second sidewalls are smaller in height than the first sidewalls.
摘要翻译：半导体器件包括：形成在半导体衬底中的第一导电类型的第一区域上的第一MIS晶体管; 以及形成在半导体衬底中的第二导电类型的第二区域上的第二MIS晶体管。第一MIS晶体管具有形成在第一区域上的第一栅极绝缘膜和第一栅电极，形成在第一栅电极的侧面上的第一侧壁和形成在第一区域的部分中的由硅制成的第一源极/漏极区域。第二MIS晶体管具有形成在第二区域上的第二栅极绝缘膜和第二栅电极，形成在第二栅电极的侧面上的第二侧壁和包括在第二区域的部分中形成的硅锗的第二源极/漏极区域。第二侧壁的高度比第一侧壁小。

18. 发明申请

US20070284670A1 Semiconductor device and fabrication method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070284670A1
公开(公告)日：2007-12-13
申请号：US11715437
申请日：2007-03-08
申请人： Kazuhiko Yamamoto , Hiromasa Fujimoto , Takafumi Kotani
发明人： Kazuhiko Yamamoto , Hiromasa Fujimoto , Takafumi Kotani
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/823443 , H01L21/82345 , H01L21/823835 , H01L21/823842
摘要： A semiconductor device has a transistor of a first conductivity type formed on a semiconductor substrate and having a first gate insulating film and a first gate electrode and a transistor of a second conductivity type having a second gate insulating film and a second gate electrode. The first gate electrode is a metal gate electrode having a metal film and the second gate electrode is a fully-silicided gate electrode made of a silicide film.
摘要翻译：半导体器件具有形成在半导体衬底上并具有第一栅极绝缘膜和第一栅极电极的第一导电类型晶体管和具有第二栅极绝缘膜和第二栅电极的第二导电类型晶体管。第一栅电极是具有金属膜的金属栅电极，第二栅电极是由硅化物膜制成的全硅化栅电极。

19. 发明申请

US20070131979A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20070131979A1
公开(公告)日：2007-06-14
申请号：US11563417
申请日：2006-11-27
申请人： Hiromasa FUJIMOTO
发明人： Hiromasa FUJIMOTO
IPC分类号： H01L29/768 , H01L27/148
CPC分类号： H01L27/115 , H01L27/11521
摘要： A memory cell array of a NOR type flash memory is constructed by arranging memory cell transistors in a matrix, each of the memory cell transistors includes a contact connecting a semiconductor substrate to an overlayer wire. Columns of the memory cell transistors are isolated from one another by shallow trench isolations. The height of top surface of a filling oxide film in the shallow trench isolation which is adjacent to each drain contact is equal to that of top surface of the drain region. The top surface of a filling oxide film in the shallow trench isolation which is adjacent to each channel region is higher than a top surface of the semiconductor substrate in the channel region.
摘要翻译： NOR型闪速存储器的存储单元阵列是通过将存储单元晶体管布置在矩阵中而构成的，每个存储单元晶体管包括将半导体衬底连接到覆盖线的触点。存储单元晶体管的列通过浅沟槽隔离彼此隔离。与每个漏极接触相邻的浅沟槽隔离物中的填充氧化膜的顶表面的高度等于漏区的顶表面的高度。与沟道区相邻的浅沟槽隔离中的填充氧化膜的顶面高于沟道区的半导体衬底的上表面。

20. 发明申请

US20060170064A1 Semiconductor memory device having a gate electrode and a diffusion layer and a manufacturing method thereof 审中-公开
标题翻译：具有栅电极和扩散层的半导体存储器件及其制造方法
公开(公告)号：US20060170064A1
公开(公告)日：2006-08-03
申请号：US11396584
申请日：2006-04-04
申请人： Keisuke Yonehama , Eiji Sakagami , Hiromasa Fujimoto , Naoki Koido
发明人： Keisuke Yonehama , Eiji Sakagami , Hiromasa Fujimoto , Naoki Koido
IPC分类号： H01L29/76 , H01L21/82
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/40114 , H01L29/42324
摘要： A semiconductor memory device having a gate electrode and a diffusion layer, comprising a plurality of memory cells each of which including the gate electrode and the diffusion layers; a first contact layer connected to one of the diffusion layer of the memory cell; a second contact layer connected to the first contact layer; a bit line connected to the second contact layer; and a conductive layer connected to at least two of the diffusion layers that are other than the diffusion layer connected to the first contact layer, at least two of the diffusion layers being arranged in a direction vertical to the bit line, a height of the conductive layer substantially being same as a height of the first contact layer.
摘要翻译：一种具有栅电极和扩散层的半导体存储器件，包括多个存储单元，每个存储单元包括栅电极和扩散层; 连接到所述存储单元的所述扩散层之一的第一接触层; 连接到所述第一接触层的第二接触层; 连接到第二接触层的位线; 以及与至少两个扩散层连接的导电层，其不同于与第一接触层连接的扩散层，至少两个扩散层沿垂直于位线的方向排列，导电层的高度层基本上与第一接触层的高度相同。

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