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11. 发明申请

US20050149701A1 Method, apparatus and system for pair-wise minimum and minimum mask instructions 审中-公开
标题翻译：用于成对的最小和最小掩模指令的方法，装置和系统
公开(公告)号：US20050149701A1
公开(公告)日：2005-07-07
申请号：US10745864
申请日：2003-12-24
申请人： Inching Chen , Dean Macri , Herbert Hum
发明人： Inching Chen , Dean Macri , Herbert Hum
IPC分类号： G06F9/00 , G06F9/302
CPC分类号： G06F9/3001 , G06F9/30021 , G06F9/30036
摘要： A method, apparatus, and system for pair-wise minimum and minimum mask instructions are generally presented.
摘要翻译：通常呈现用于成对的最小和最小掩模指令的方法，装置和系统。

12. 发明授权

US09311085B2 Compiler assisted low power and high performance load handling based on load types 有权
标题翻译：基于负载类型的编译器辅助低功耗和高性能负载处理
公开(公告)号：US09311085B2
公开(公告)日：2016-04-12
申请号：US11967230
申请日：2007-12-30
申请人： Tingting Sha , Chris Wilkerson , Herbert Hum , Alaa R. Alameldeen
发明人： Tingting Sha , Chris Wilkerson , Herbert Hum , Alaa R. Alameldeen
IPC分类号： G06F9/312 , G06F9/30 , G06F9/45 , G06F9/38
CPC分类号： G06F9/30043 , G06F8/41 , G06F8/4442 , G06F9/30047 , G06F9/30185 , G06F9/3826 , G06F9/3891
摘要： A method and apparatus for handling low power and high performance loads is herein described. Software, such as a compiler, is utilized to identify producer loads, consumer reuse loads, and consumer forwarded loads. Based on the identification by software, hardware is able to direct performance of the load directly to a load value buffer, a store buffer, or a data cache. As a result, accesses to cache are reduced, through direct loading from load and store buffers, without sacrificing load performance.
摘要翻译：这里描述了用于处理低功率和高性能负载的方法和装置。使用诸如编译器的软件来识别生产者负载，消费者重用负载和消费者转发的负载。基于软件识别，硬件能够将负载的性能直接引导到负载值缓冲器，存储缓冲器或数据高速缓存。因此，通过从加载和存储缓冲区直接加载，可以减少对缓存的访问，而不会牺牲负载性能。

13. 发明申请

US20130314425A1 DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS 审中-公开
标题翻译：在非对称加工元素中分配任务
公开(公告)号：US20130314425A1
公开(公告)日：2013-11-28
申请号：US13954979
申请日：2013-07-31
申请人： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
发明人： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC分类号： G06T1/20
CPC分类号： G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system
摘要翻译：控制多个不对称核心之间的功率和处理的技术。在一个实施例中，根据系统的性能和功率需求，一个或多个非对称核被功率管理以在多个核之间迁移进程或线程

14. 发明申请

US20130246712A1 Methods And Apparatuses For Efficient Load Processing Using Buffers 审中-公开
标题翻译：使用缓冲器高效加载处理的方法和设备
公开(公告)号：US20130246712A1
公开(公告)日：2013-09-19
申请号：US13886467
申请日：2013-05-03
申请人： WEI LIU , YOUFENG WU , CHRISTOPHER WILKERSON , HERBERT HUM
发明人： WEI LIU , YOUFENG WU , CHRISTOPHER WILKERSON , HERBERT HUM
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F8/4442 , G06F9/30043 , G06F9/3826 , G06F9/383 , Y02D10/13
摘要： Various embodiments of the invention concern methods and apparatuses for power and time efficient load handling. A compiler may identify producer loads, consumer reuse loads, consumer forwarded loads, and producer/consumer hybrid loads. Based on this identification, performance of the load may be efficiently directed to a load value buffer, store buffer, data cache, or elsewhere. Consequently, accesses to cache are reduced, through direct loading from load value buffers and store buffers, thereby efficiently processing the loads.
摘要翻译：本发明的各种实施例涉及用于功率和时间有效的负载处理的方法和装置。编译器可以识别生产者负载，消费者重用负载，消费者转发负载以及生产者/消费者混合负载。基于该识别，可以将负载的性能有效地指向负载值缓冲器，存储缓冲器，数据高速缓存或其他位置。因此，通过从负载值缓冲区和存储缓冲区的直接加载，减少对高速缓存的访问，从而有效地处理负载。

15. 发明授权

US08099587B2 Compressing and accessing a microcode ROM 有权
标题翻译：压缩和访问微码ROM
公开(公告)号：US08099587B2
公开(公告)日：2012-01-17
申请号：US11186240
申请日：2005-07-20
申请人： Youfeng Wu , Sangwook Kim , Mauricio Breternitz, Jr. , Herbert Hum
发明人： Youfeng Wu , Sangwook Kim , Mauricio Breternitz, Jr. , Herbert Hum
IPC分类号： G06F9/00
CPC分类号： G06F12/06 , G06F8/4436 , G06F9/30178 , G06F2212/401
摘要： An arrangement is provided for compressing microcode ROM (“uROM”) in a processor and for efficiently accessing a compressed “uROM”. A clustering-based approach may be used to effectively compress a uROM. The approach groups similar columns of microcode into different clusters and identifies unique patterns within each cluster. Only unique patterns identified in each cluster are stored in a pattern storage. Indices, which help map an address of a microcode word (“uOP”) to be fetched from a uROM to unique patterns required for the uOP, may be stored in an index storage. Typically it takes a longer time to fetch a uOP from a compressed uROM than from an uncompressed uROM. The compressed uROM may be so designed that the process of fetching a uOP (or uOPs) from a compressed uROM may be fully-pipelined to reduce the access latency.
摘要翻译：提供了一种用于在处理器中压缩微代码ROM（“uROM”）并有效访问压缩的“uROM”的装置。可以使用基于聚类的方法来有效地压缩uROM。该方法将相似的微代码列组合成不同的集群，并识别每个集群内的唯一模式。每个集群中唯一标识的模式都存储在模式存储中。帮助将从uROM获取的微代码字（“uOP”）的地址映射到uOP所需的唯一模式的索引可以存储在索引存储器中。通常，从压缩的uROM获取uop比从未压缩的uROM获取更长的时间。压缩的uROM可以被设计成使得从压缩的uROM获取uop（或uop）的过程可以被完全流水线化以减少访问等待时间。

16. 发明申请

US20090222654A1 Distribution of tasks among asymmetric processing elements 有权
标题翻译：不对称处理要素之间的任务分配
公开(公告)号：US20090222654A1
公开(公告)日：2009-09-03
申请号：US12220092
申请日：2008-07-22
申请人： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
发明人： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC分类号： G06F1/24 , G06F1/32 , G06F1/08
CPC分类号： G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
摘要翻译：控制多个不对称核心之间的功率和处理的技术。在一个实施例中，根据系统的性能和功率需求，一个或多个非对称核被功率管理以在多个核之间迁移进程或线程。

17. 发明申请

US20080005482A1 Requester-generated forward the late conflicts in a cache coherency protocol 失效
标题翻译：请求者产生转发高速缓存一致性协议中的后期冲突
公开(公告)号：US20080005482A1
公开(公告)日：2008-01-03
申请号：US11479179
申请日：2006-06-30
申请人： Robert Beers , Herbert Hum
发明人： Robert Beers , Herbert Hum
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0828
摘要： A method for resolving data request conflicts in a cache coherency protocol for multiple caching agents using requester-generated data forwards. In one embodiment, a caching agent stores information used to auto-generate a forward of data received in response to a data request.
摘要翻译：一种用于使用请求者生成的数据转发来解决多个缓存代理的高速缓存一致性协议中的数据请求冲突的方法。在一个实施例中，高速缓存代理存储用于自动生成响应于数据请求而接收的数据的前向的信息。

18. 发明申请

US20070047584A1 Interleaving data packets in a packet-based communication system 有权
标题翻译：在数据包通信系统中交织数据包
公开(公告)号：US20070047584A1
公开(公告)日：2007-03-01
申请号：US11211063
申请日：2005-08-24
申请人： Aaron Spink , Herbert Hum
发明人： Aaron Spink , Herbert Hum
IPC分类号： G01R31/08 , H04J3/24
CPC分类号： H04L49/9057 , H04L12/66 , H04L49/9021 , H04L49/9042 , H04L49/9094
摘要： In one embodiment, the present invention includes a method for receiving a first portion of a first packet at a first agent and determining whether the first portion is an interleaved portion based on a value of an interleave indicator. The interleave indicator may be sent as part of the first portion. In such manner, interleaved packets may be sent within transmission of another packet, such as a lengthy data packet, providing improved processing capabilities. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在第一代理处接收第一分组的第一部分并基于交织指示符的值确定第一部分是交织部分的方法。交错指示符可以作为第一部分的一部分发送。以这种方式，交织的分组可以在另一个分组（例如冗长的数据分组）的传输内发送，从而提供改进的处理能力。描述和要求保护其他实施例。

19. 发明申请

US20070002760A1 Virtualization of pin functionality in a point-to-point interface 有权
标题翻译：在点对点接口中实现引脚功能的虚拟化
公开(公告)号：US20070002760A1
公开(公告)日：2007-01-04
申请号：US11173643
申请日：2005-06-30
申请人： Keshavan Tiruvallur , David Poisner , Herbert Hum , Frank Binns , David Hill , Robert Greiner , Raymond Tetrick
发明人： Keshavan Tiruvallur , David Poisner , Herbert Hum , Frank Binns , David Hill , Robert Greiner , Raymond Tetrick
IPC分类号： H04J1/16
CPC分类号： G06F17/5068 , G06F17/5045
摘要： Architectures and techniques that allow legacy pin functionality to be replaced with a “virtual wire” that may communicate information that would otherwise be communicated by a wired interface. A message may be passed between a system controller and a processor that includes a virtual wire value and a virtual wire change indicator. The virtual wire value may include a signal corresponding to one or more pins that have been eliminated from the physical interface and the virtual wire change value may include an indication of whether the virtual wire value has changed. The combination of the virtual wire value and the virtual wire change indicator may allow multiple physical pins to be replaced by message values.
摘要翻译：允许传统引脚功能被替换为“虚拟线”的架构和技术，“虚拟线”可以传达否则将由有线接口传送的信息。可以在系统控制器和包括虚拟线路值和虚拟换线指示器的处理器之间传递消息。虚拟线值可以包括对应于已经从物理接口消除的一个或多个引脚的信号，并且虚拟线更改值可以包括虚拟线值是否已经改变的指示。虚拟线路值和虚拟线路变化指示器的组合可以允许多个物理引脚被消息值替换。

20. 发明申请

US20050144388A1 Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information 有权
标题翻译：处理器和内存控制器能够在采用压缩缓存行的信息量的计算系统中使用
公开(公告)号：US20050144388A1
公开(公告)日：2005-06-30
申请号：US10750715
申请日：2003-12-31
申请人： Chris Newburn , Ram Huggahalli , Herbert Hum , Ali-Reza Adl-Tabatabai , Anwar Ghuloum
发明人： Chris Newburn , Ram Huggahalli , Herbert Hum , Ali-Reza Adl-Tabatabai , Anwar Ghuloum
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0802 , G06F12/0886 , G06F2212/401
摘要： A memory controller is described that comprises a compression map cache. The compression map cache is to store information that identifies a cache line's worth of information that has been compressed with another cache line's worth of information. A processor and a memory controller integrated on a same semiconductor die is also described. The memory controller comprises a compression map cache. The compression map cache is to store information that identifies a cache line's worth of information that has been compressed with another cache line's worth of information.
摘要翻译：描述了包括压缩映射高速缓存的存储器控制器。压缩映射缓存用于存储标识缓存行的信息值的信息，该信息已被另一个高速缓存行的信息压缩。还描述了集成在同一半导体管芯上的处理器和存储器控制器。存储器控制器包括压缩映射高速缓存。压缩映射缓存用于存储标识缓存行的信息值的信息，该信息已被另一个高速缓存行的信息压缩。

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