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11. 发明授权

US12045692B2 Squid stack pulse height bias-level sensor for reciprocal quantum logic 有权
公开(公告)号：US12045692B2
公开(公告)日：2024-07-23
申请号：US17736646
申请日：2022-05-04
申请人： Haitao O. Dai , Max E. Nielsen , Alexander Louis Braun , Daniel George Dosch , Kurt Pleim , Charles Ryan Wallace
发明人： Haitao O. Dai , Max E. Nielsen , Alexander Louis Braun , Daniel George Dosch , Kurt Pleim , Charles Ryan Wallace
IPC分类号： G06N10/40 , G01R33/035
CPC分类号： G06N10/40 , G01R33/0354
摘要： An output-amplifier-based reciprocal quantum logic (RQL) bias-level sensor is used to measure and/or calibrate bias parameters of AC and/or DC bias signals provided to RQL circuitry. The bias signals can include an output amplifier output bias current. The bias-level sensor includes a stack of DC SQUIDs that are supplied their inputs from outputs of respective Josephson transmission lines (JTLs) to which the SQUIDs are transformer-coupled. Staging relative strengths of the bias taps of the JTLs, or the critical currents of the Josephson junctions in the DC SQUIDs, allows an output voltage signal of the bias-level sensor to be indicative of whether a provided bias value is an improvement or optimization of the bias value when varied over a range. The outputs of two such bias-level sensors driven by I and Q clocks can be compared to adjust AC bias amplitudes of the clocks. Relative clock phase can be similarly adjusted.

12. 发明公开

US20230363292A1 BIAS-LEVEL SENSORS FOR RECIPROCAL QUANTUM LOGIC 审中-公开
公开(公告)号：US20230363292A1
公开(公告)日：2023-11-09
申请号：US17736463
申请日：2022-05-04
申请人： MAX E. NIELSEN , ALEXANDER LOUIS BRAUN , DANIEL GEORGE DOSCH , KURT PLEIM , HAITAO O. DAI , CHARLES R. WALLACE
发明人： MAX E. NIELSEN , ALEXANDER LOUIS BRAUN , DANIEL GEORGE DOSCH , KURT PLEIM , HAITAO O. DAI , CHARLES R. WALLACE
IPC分类号： G06N10/40 , H01L39/22
CPC分类号： H01L39/223 , G06N10/40
摘要： Reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors, or samplers, include Josephson transmission lines (JTLs) or logic gates having strengthened or weakened bias taps as compared to bias taps of JTLs or logic gates in the operational RQL circuitry. Sampler JTLs or logic gates with weakened bias taps to AC clock resonators can have lower limits of their operational ranges placed near an optimal bias point at the centroid of the operating region of the operational RQL circuitry. Staging relative strengths of the bias taps of the samplers in an ensemble of samplers allows for outputs of wrapper circuitry to be indicative of whether a provided bias value is an improvement or optimization of the bias value when varied over a range.

13. 发明授权

US11569976B2 Superconducting isochronous receiver system 有权
公开(公告)号：US11569976B2
公开(公告)日：2023-01-31
申请号：US17340814
申请日：2021-06-07
申请人： Brian Lee Koehler , Corey Arthur Kegerreis , Haitao O. Dai , Quentin P. Herr
发明人： Brian Lee Koehler , Corey Arthur Kegerreis , Haitao O. Dai , Quentin P. Herr
IPC分类号： H04L7/00 , G06F13/40 , G06N10/00 , H03K19/195
摘要： One example includes an isochronous receiver system. The system includes a pulse receiver configured to receive an input data signal from a transmission line and to convert the input data signal to a pulse signal. The system also includes a converter system comprising a phase converter system. The phase converter system includes a plurality of pulse converters associated with a respective plurality of sampling windows across a period of an AC clock signal. At least two of the sampling windows overlap at any given phase of the AC clock signal, such that the converter system is configured to generate an output pulse signal that is phase-aligned with at least one of a plurality of sampling phases of the AC clock signal based on associating the pulse signal with at least two of the sampling windows.

14. 发明申请

US20140035670A1 FET PAIR BASED PHYSICALLY UNCLONABLE FUNCTION (PUF) CIRCUIT WITH A CONSTANT COMMON MODE VOLTAGE 有权
标题翻译：具有恒定通用模式电压的基于FET对的物理不可靠功能（PUF）电路
公开(公告)号：US20140035670A1
公开(公告)日：2014-02-06
申请号：US13566805
申请日：2012-08-03
申请人： Howard H. Chi , Haitao O. Dai , Kai D. Feng , Donald J. Papae
发明人： Howard H. Chi , Haitao O. Dai , Kai D. Feng , Donald J. Papae
IPC分类号： H03F3/45
CPC分类号： G06F7/588 , G09C1/00 , H04L9/0866 , H04L9/3278 , H04L2209/12
摘要： A FET pair based physically unclonable function (PUF) circuit with a constant common mode voltage and methods of use are disclosed. The circuit includes a first n-type field effect transistor (NFET) and a second NFET. The circuit also includes a first load resistor coupled to the first NFET by a first p-type field effect transistor (PFET) and a second load resistor coupled to the second NFET by a second PFET. The circuit further comprises a closed loop, wherein the closed loop creates a constant common mode voltage.
摘要翻译：公开了一种具有恒定共模电压的物理不可克隆功能（PUF）电路和使用方法的FET对。电路包括第一n型场效应晶体管（NFET）和第二NFET。电路还包括通过第一p型场效应晶体管（PFET）耦合到第一NFET的第一负载电阻器和通过第二PFET耦合到第二NFET的第二负载电阻器。电路还包括闭环，其中闭环产生恒定的共模电压。

15. 发明申请

US20130241652A1 UTILIZING A SENSE AMPLIFIER TO SELECT A SUITABLE CIRCUIT 失效
标题翻译：使用感应放大器选择适合的电路
公开(公告)号：US20130241652A1
公开(公告)日：2013-09-19
申请号：US13418961
申请日：2012-03-13
申请人： Howard H. Chi , Haitao O. Dai , Kai D. Feng , Donald J. Papae
发明人： Howard H. Chi , Haitao O. Dai , Kai D. Feng , Donald J. Papae
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45609 , H03F3/68 , H03F2200/408 , H03F2200/78
摘要： Embodiments of the present invention provide an approach for utilizing a sense amplifier to select a suitable circuit, wherein a suitable circuit generates a voltage that is greater than or equal to a configurable reference voltage. An amplifier gain selector selects a voltage gain of a sense amplifier having input terminals, auxiliary inputs, an output, an array of resistive loads, and the amplifier gain selector. Auxiliary inputs are utilized to nullify direct current (DC) offset voltage of the sense amplifier. Combinatorial logic circuitry connects the input terminals of the sense amplifier to output terminals of a circuit that is within a group of circuits. A comparator circuit determines if the circuit generates a voltage greater than or equal to a configurable reference voltage, based on the output of the sense amplifier.
摘要翻译：本发明的实施例提供了一种利用读出放大器来选择合适电路的方法，其中合适的电路产生大于或等于可配置参考电压的电压。放大器增益选择器选择具有输入端，辅助输入，输出，电阻性负载阵列和放大器增益选择器的读出放大器的电压增益。辅助输入用于消除读出放大器的直流（DC）偏移电压。组合逻辑电路将读出放大器的输入端连接到一组电路内的电路的输出端。比较器电路基于读出放大器的输出来确定电路是否产生大于或等于可配置参考电压的电压。

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