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11. 发明授权

US06551897B2 Wafer trench article and process 有权
公开(公告)号：US06551897B2
公开(公告)日：2003-04-22
申请号：US09993968
申请日：2001-11-16
申请人： Patrick Anthony Begley , Donald Frank Hemmenway , George Bajor , Anthony Lee Rivoli , Jeanne Marie McNamara , Michael Sean Carmody , Dustin Alexander Woodbury
发明人： Patrick Anthony Begley , Donald Frank Hemmenway , George Bajor , Anthony Lee Rivoli , Jeanne Marie McNamara , Michael Sean Carmody , Dustin Alexander Woodbury
IPC分类号： H01L21762
CPC分类号： H01L21/7624 , H01L21/76264 , H01L21/76275 , H01L21/76281 , H01L21/76286
摘要： A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.

12. 发明授权

US5807780A High frequency analog transistors method of fabrication and circuit implementation 失效
标题翻译：高频模拟晶体管的制造和电路实现方法
公开(公告)号：US5807780A
公开(公告)日：1998-09-15
申请号：US462851
申请日：1995-06-05
申请人： Christopher K. Davis , George Bajor , James D. Beasom , Thomas L. Crandell , Taewon Jung , Anthony L. Rivoli
发明人： Christopher K. Davis , George Bajor , James D. Beasom , Thomas L. Crandell , Taewon Jung , Anthony L. Rivoli
IPC分类号： H01L29/73 , H01L21/331 , H01L21/74 , H01L21/8228 , H01L21/84 , H01L27/06 , H01L27/082 , H01L27/12 , H01L29/08 , H01L29/167 , H01L29/732 , H01L29/808 , H01L29/8605 , H01L21/8222
CPC分类号： H01L29/66272 , H01L21/8228 , H01L21/82285 , H01L21/84 , H01L27/0623 , H01L27/082 , H01L27/0826 , H01L27/1203 , H01L29/0821 , H01L29/167 , H01L29/7325 , H01L29/808 , H01L29/8605
摘要： A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.
摘要翻译：用于介质隔离的高频互补模拟双极和CMOS晶体管的制造工艺。多晶硅非本征基极，具有在内部基底形成之后形成的侧壁间隔物的多晶硅发射体提供高电流增益，大的发射极到基极击穿电压，大的早期电压和高截止频率。

13. 发明授权

US5933746A Process of forming trench isolation device 失效
标题翻译：形成沟槽隔离装置的工艺
公开(公告)号：US5933746A
公开(公告)日：1999-08-03
申请号：US637937
申请日：1996-04-23
申请人： Patrick Anthony Begley , Donald Frank Hemmenway , George Bajor , Anthony Lee Rivoli , Jeanne Marie McNamara , Michael Sean Carmody , Dustin Alexander Woodbury
发明人： Patrick Anthony Begley , Donald Frank Hemmenway , George Bajor , Anthony Lee Rivoli , Jeanne Marie McNamara , Michael Sean Carmody , Dustin Alexander Woodbury
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/7624 , H01L21/76264 , H01L21/76275 , H01L21/76281 , H01L21/76286
摘要： A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.
摘要翻译：键合晶片100具有具有限定器件区域18的隔离沟槽30的器件衬底16.在填充沟槽30之前去除氧化物骨骼结构。沟槽中的空隙36与沟槽的顶部间隔开。沟槽被氧化物层30覆盖并填充有多晶硅34.包括CVD衬垫氧化物层和氮化硅50的LOCOS掩模结构覆盖沟槽和相邻的器件衬底区域。

14. 发明授权

US5892264A High frequency analog transistors, method of fabrication and circuit implementation 失效
标题翻译：高频模拟晶体管，制造方法和电路实现
公开(公告)号：US5892264A
公开(公告)日：1999-04-06
申请号：US786569
申请日：1997-01-21
申请人： Christopher K. Davis , George Bajor , James D. Beasom , Thomas L. Crandell , Taewon Jung , Anthony L. Rivoli
发明人： Christopher K. Davis , George Bajor , James D. Beasom , Thomas L. Crandell , Taewon Jung , Anthony L. Rivoli
IPC分类号： H01L21/8228 , H01L21/84 , H01L27/082 , H01L27/12 , H01L29/00
CPC分类号： H01L27/0826 , H01L21/8228 , H01L21/84 , H01L27/1203
摘要： A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.
摘要翻译：用于介质隔离的高频互补模拟双极和CMOS晶体管的制造工艺。多晶硅非本征基极，具有在内部基底形成之后形成的侧壁间隔物的多晶硅发射体提供高电流增益，大的发射极到基极击穿电压，大的早期电压和高截止频率。

15. 发明授权

US5668397A High frequency analog transistors, method of fabrication and circuit implementation 失效
标题翻译：高频模拟晶体管，制造方法和电路实现
公开(公告)号：US5668397A
公开(公告)日：1997-09-16
申请号：US131369
申请日：1993-10-04
申请人： Christopher K. Davis , George Bajor , James D. Beasom , Thomas L. Crandell , Taewon Jung , Anthony L. Rivoli
发明人： Christopher K. Davis , George Bajor , James D. Beasom , Thomas L. Crandell , Taewon Jung , Anthony L. Rivoli
IPC分类号： H01L29/73 , H01L21/331 , H01L21/74 , H01L21/8228 , H01L21/84 , H01L27/06 , H01L27/082 , H01L27/12 , H01L29/08 , H01L29/167 , H01L29/732 , H01L29/808 , H01L29/8605 , H01L29/00
CPC分类号： H01L29/66272 , H01L21/8228 , H01L21/82285 , H01L21/84 , H01L27/0623 , H01L27/082 , H01L27/0826 , H01L27/1203 , H01L29/0821 , H01L29/167 , H01L29/7325 , H01L29/808 , H01L29/8605
摘要： A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.
摘要翻译：用于介质隔离的高频互补模拟双极和CMOS晶体管的制造工艺。多晶硅非本征基极，具有在内部基底形成之后形成的侧壁间隔物的多晶硅发射体提供高电流增益，大的发射极到基极击穿电压，大的早期电压和高截止频率。

16. 发明授权

US5633180A Method of forming P-type islands over P-type buried layer 失效
标题翻译：在P型掩埋层上形成P型岛的方法
公开(公告)号：US5633180A
公开(公告)日：1997-05-27
申请号：US456727
申请日：1995-06-01
申请人： George Bajor
发明人： George Bajor
IPC分类号： H01L21/74 , H01L21/265
CPC分类号： H01L21/74
摘要： A method of fabricating a vertical conductive region in a semiconductor device in which plural epitaxial layers are successively grown on a substrate and a dopant is implanted into each epitaxial layer before growing the next layer. A fast vertical transistor operable in the GHz range and at high voltage (e.g., more than about 10 volts) is fabricated by growing plural epitaxial layers, each with a thickness less than about 2.5 microns until the desired height of the vertical conductive region is reached. Sections of the transistor's collector and an adjacent sinker are implanted through each epitaxial layer before the next layer is grown. Annealing after ion implant joins the sinker and collector sections in each layer with the corresponding sinker and collector sections in adjacent layers to form unitary structures in the transistor. Each layer is thin enough for the dopant to penetrate to the bottom of the layer using conventional implant energy. The manufacturing process does not limit the height of the sinker or collector.
摘要翻译：在半导体器件中制造垂直导电区域的方法，其中在衬底上连续生长多个外延层，并且在生长下一层之前将掺杂剂注入到每个外延层中。可以通过生长多个外延层来制造在GHz范围和高电压（例如，大于约10伏特）下工作的快速垂直晶体管，每个外延层具有小于约2.5微米的厚度，直到达到所需垂直导电区域的高度。在下一层生长之前，通过每个外延层注入晶体管集电极和相邻沉降片的部分。离子注入后的退火将每个层中的沉降片和集电极部分与相邻层中的相应沉降片和集电极部分结合，以在晶体管中形成单一结构。每个层都足够薄以使掺杂剂使用常规的注入能量渗透到层的底部。制造过程不限制沉降片或收集器的高度。

17. 发明授权

US5603779A Bonded wafer and method of fabrication thereof 失效
标题翻译：粘合晶片及其制造方法
公开(公告)号：US5603779A
公开(公告)日：1997-02-18
申请号：US443242
申请日：1995-05-17
申请人： Jack H. Linn , George Bajor , George V. Rouse
发明人： Jack H. Linn , George Bajor , George V. Rouse
IPC分类号： H01L21/20
CPC分类号： H01L21/2007 , Y10S148/012 , Y10S438/974
摘要： A bonded wafer with a bond junction having low resistivity due to the low level of oxides at the bond junction. A plasma that removes native oxide layers from wafers is exposed to the wafers. The plasma forms a hydrophobic polymer seal on the wafers, inhibiting subsequent native oxide growth upon exposure to air. The polymer seal on the wafers to be bonded are pressed together and the wafers are annealed to form the bonded wafer in a non-oxidizing ambient. The bond junction formed is primarily silicon to silicon and silicon to carbon bonds.
摘要翻译：具有键合结的键合晶片由于在键合结处的氧化物水平低而具有低电阻率。从晶片去除原生氧化物层的等离子体暴露于晶片。等离子体在晶片上形成疏水聚合物密封，在暴露于空气中时抑制随后的天然氧化物生长。将要接合的晶片上的聚合物密封件压在一起，并且将晶片退火以在非氧化环境中形成接合晶片。所形成的键合键主要是硅与硅和硅与碳键。

18. 发明授权

US5382541A Method for forming recessed oxide isolation containing deep and shallow trenches 失效
标题翻译：用于形成包含深和浅沟槽的凹陷氧化物隔离的方法
公开(公告)号：US5382541A
公开(公告)日：1995-01-17
申请号：US935765
申请日：1992-08-26
申请人： George Bajor , Anthony L. Rivoli
发明人： George Bajor , Anthony L. Rivoli
IPC分类号： H01L21/762 , H01L21/763 , H01L21/302
CPC分类号： H01L21/76224 , H01L21/76264 , H01L21/763 , H01L21/76275 , H01L21/76283
摘要： Recessed isolation oxide is deposited in shallow trenches simultaneoulsy with oxide deposition in deep isolation trenches. A single planarization of both trench fillings provides efficient recessed isolation oxide without bird's beak or bird 's head problems of LOCOS isolation oxide. Self-aligned trench filling by successive conformal depositions of oxide and polysilicon followed by planarization to remove polysilicon away from the trenches. The the remaining polysilicon may be used as an oxide etch mask to remove all of the oxide except in the trenches.
摘要翻译：嵌入的隔离氧化物沉积在浅沟槽中，同时在深隔离沟槽中沉积氧化物。两个沟槽填充物的单一平面化提供了有效的凹陷隔离氧化物，而没有鸟喙或LOCOS隔离氧化物的鸟头问题。通过氧化物和多晶硅的连续共形沉积的自对准沟槽填充，随后进行平面化以从沟槽移除多晶硅。剩余的多晶硅可以用作氧化物蚀刻掩模以除去除了沟槽中的所有氧化物。

19. 发明授权

US4670970A Method for making a programmable vertical silicide fuse 失效
标题翻译：制造可编程垂直硅化物保险丝的方法
公开(公告)号：US4670970A
公开(公告)日：1987-06-09
申请号：US722584
申请日：1985-04-12
申请人： George Bajor
发明人： George Bajor
IPC分类号： H01L23/525 , H01L21/385 , H01L21/441
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： The present invention provides an improved method of forming semiconductor fuses involving the use of silicide formation by a low temperature process which avoids heat related damage to other device components and circuitry and which provides better electrical reliability than fuses formed by alternative porcesses. According to the present invention, silicides of noble and refractory metals can be formed by solid phase diffusion to form vertical fuses which are conductive after silicide formation.
摘要翻译：本发明提供了一种形成半导体熔丝的改进方法，其涉及通过低温工艺使用硅化物形成，其避免了与其它器件部件和电路相关的热相关损伤，并且与提供由替代过程形成的熔断器相比提供更好的电可靠性。根据本发明，可以通过固相扩散形成贵金属和难熔金属的硅化物，以形成在硅化物形成之后导电的垂直熔丝。

20. 发明授权

US4606936A Stress free dielectric isolation technology 失效
标题翻译：无压介电隔离技术
公开(公告)号：US4606936A
公开(公告)日：1986-08-19
申请号：US723581
申请日：1985-04-12
申请人： George Bajor , Charles Messmer
发明人： George Bajor , Charles Messmer
IPC分类号： H01L21/316 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76297 , H01L21/31604
摘要： Stress is eliminated between a dielectrically passivated silicon wafer and a thick polycrystalline silicon layer by depositing a low melting transition layer such as a doped silica glass over the passivated silicon wafer.
摘要翻译：通过在钝化硅晶片上沉积低熔点过渡层（例如掺杂二氧化硅玻璃），在介电钝化硅晶片和厚多晶硅层之间消除应力。

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