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11. 发明授权

US06809589B2 Low voltage large swing/high linearity analog buffer with servo amplifier and feedback loop 有权
公开(公告)号：US06809589B2
公开(公告)日：2004-10-26
申请号：US10460066
申请日：2003-06-12
申请人： Gabriele Manganaro
发明人： Gabriele Manganaro
IPC分类号： H03F345
CPC分类号： G05F1/56 , H03F1/34 , H03F3/347 , H03F3/45098 , H03F3/45107 , H03F2203/45322 , H03F2203/45326 , H03F2203/45356
摘要： An analog buffer with low harmonic distortion and low power supply voltage buffers a signal with wide voltage swing. The lower output voltage swing is increased, by adding a voltage level shifter to the feedback path of a servo. The upper output voltage swing is increased by coupling the output load to Vdd.

12. 发明授权

US06570410B2 Feed-forward approach for timing skew in interleaved and double-sampled circuits 有权
公开(公告)号：US06570410B2
公开(公告)日：2003-05-27
申请号：US10105681
申请日：2002-03-25
申请人： Gabriele Manganaro
发明人： Gabriele Manganaro
IPC分类号： G11C2702
CPC分类号： G11C27/026 , H03K5/1515 , H03M1/1215
摘要： The present invention relates to a clock generator circuit which comprises a clock generator subcircuit which is operable to generate two clock signals having approximately the same frequency for use in sampling an analog signal in a generally alternating fashion. The clock generator circuit further comprises a pre-phase clock generator subcircuit associated with the clock generator subcircuit which is operable to generate two pre-phase clock signals, wherein each are associated with a respective one of the two clock signals generated by the clock generator subcircuit. In the pre-phase clock generator circuit, a signal transition of each of the pre-phase clock signals occurs before a signal transition of the respective clock signal generated by the clock generator subcircuit; in addition, a timing of a falling edge of the pre-phase clock signals is dictated by a global clock signal. Thus the clock generator circuit avoids sampling error in a double-sampled sample and hold circuit and harmonic distortion associated therewith.

13. 发明授权

US07345530B1 Regulated switch driving scheme in switched-capacitor amplifiers with opamp-sharing 有权
标题翻译：具有运算放大器共享的开关电容放大器的调节开关驱动方案
公开(公告)号：US07345530B1
公开(公告)日：2008-03-18
申请号：US11421716
申请日：2006-06-01
申请人： Jipeng Li , Matthew Courcy , Gabriele Manganaro
发明人： Jipeng Li , Matthew Courcy , Gabriele Manganaro
IPC分类号： H03F1/02
CPC分类号： H03F3/005
摘要： A switched-capacitor amplifier circuit including first and second pairs of sampling capacitors for sampling a pair of input signals includes a voltage regulator coupled to receive a first reference voltage and generate a first regulated output voltage related to the first reference voltage and independent of a first power supply voltage; a clock signal generator generating first and second clock signals referenced to the first power supply voltage and third and fourth clock signals referenced to the first regulated output voltage; and a first set of switches coupling the bottom plates of the sampling capacitors to the amplifier, the first set of switches being controlled by the third and fourth clock signals. The circuit may further include a second set of switches coupling the top plates of the sampling capacitors to the input signals, the second set of switches being controlled by the first and second clock signals.
摘要翻译：包括用于对一对输入信号进行采样的第一和第二对采样电容器的开关电容放大器电路包括耦合以接收第一参考电压并产生与第一参考电压有关的第一调节输出电压的电压调节器，并且独立于第一电源电压; 产生参考第一电源电压的第一和第二时钟信号的时钟信号发生器和参考第一调节输出电压的第三和第四时钟信号; 以及将采样电容器的底板耦合到放大器的第一组开关，第一组开关由第三和第四时钟信号控制。电路还可以包括将采样电容器的顶板耦合到输入信号的第二组开关，第二组开关由第一和第二时钟信号控制。

14. 发明授权

US07042374B1 Calibration of a current source array 有权
标题翻译：校准电流源阵列
公开(公告)号：US07042374B1
公开(公告)日：2006-05-09
申请号：US11086901
申请日：2005-03-21
申请人： Gabriele Manganaro
发明人： Gabriele Manganaro
IPC分类号： H03M1/10
CPC分类号： H03M1/1057 , H03M1/742
摘要： A current source cell includes a current source providing a first current where the first current can be calibrated, first and second switches coupled to steer the first current to respective first and second output terminals in response to respective first and second control signals, and a latch circuit generating the first and second control signals. The latch circuit drives the first and second control signals to a first logical state to cause the first and second switches to open. The first current is then calibrated. After calibration, the latch circuit drives the first and second control signals to have logical states that correspond to a data signal as triggered by a clock signal where the first and second control signals have inverse logical states. One of the first and second switches is closed to steer the first current to a respective one of the first and second output terminals.
摘要翻译：电流源单元包括提供第一电流的电流源，其中可以校准第一电流，第一和第二开关耦合以响应于相应的第一和第二控制信号而将第一电流转向相应的第一和第二输出端，以及锁存器产生第一和第二控制信号的电路。锁存电路将第一和第二控制信号驱动到第一逻辑状态，以使第一和第二开关断开。然后校准第一个电流。在校准之后，锁存电路驱动第一和第二控制信号以具有对应于由第一和第二控制信号具有反逻辑状态的时钟信号触发的数据信号的逻辑状态。关闭第一和第二开关中的一个以将第一电流转向第一和第二输出端子中的相应一个。

15. 发明授权

US07023367B1 Current steering digital to analog converter with improved dynamic linearity 有权
标题翻译：电流转向数模转换器具有改善的动态线性度
公开(公告)号：US07023367B1
公开(公告)日：2006-04-04
申请号：US11077742
申请日：2005-03-10
申请人： Gabriele Manganaro
发明人： Gabriele Manganaro
IPC分类号： H03M1/00
CPC分类号： H03M1/0614 , H03M1/742
摘要： A current source cell includes a current source providing a first current at a first node where variations of a first voltage at the first node results in variations of the first current, and first and second switches coupled between the first node and respective first and second output terminals. A control signal is coupled to selectively apply a first drive voltage to a selected one of the first and second switches to close the selected switch to steer the first current to the corresponding output terminal. The current source cell further includes a voltage adjustment circuit coupled to detect variations in the first voltage and vary the first drive voltage in response to the variations in the first voltage. The first drive voltage applied to the selected switch is varied to reduce the variations in the first voltage, thereby maintaining the first voltage at a substantially stable voltage value.
摘要翻译：电流源单元包括在第一节点处提供第一电流的电流源，其中第一节点处的第一电压的变化导致第一电流的变化，以及耦合在第一节点和相应的第一和第二输出之间的第一和第二开关终端。耦合控制信号以选择性地将第一驱动电压施加到所选择的第一和第二开关中的一个以关闭所选择的开关以将第一电流转向相应的输出端。电流源单元还包括电压调节电路，其耦合以检测第一电压的变化并响应于第一电压的变化而改变第一驱动电压。改变施加到所选开关的第一驱动电压以减小第一电压的变化，从而将第一电压保持在基本上稳定的电压值。

16. 发明授权

US6047276A Cellular neural network to implement the unfolded Chua's circuit 失效
标题翻译：细胞神经网络实现展开的蔡氏电路
公开(公告)号：US6047276A
公开(公告)日：2000-04-04
申请号：US825546
申请日：1997-03-19
申请人： Gabriele Manganaro , Mario Lavorgna , Matteo Lo Presti , Luigi Fortuna
发明人： Gabriele Manganaro , Mario Lavorgna , Matteo Lo Presti , Luigi Fortuna
IPC分类号： G06G7/26 , G06N3/063 , G06E1/00
CPC分类号： G06G7/26 , G06N3/0635
摘要： A neural cellular network for implementing a so-called Chua's circuit, and comprising at least first, second and third cells having respective first and second input terminals and respective state terminals, the first and second input terminals being to receive a first and a second reference signal, respectively, and the first cell, and the second and third cells being of mutually different types.
摘要翻译：一种用于实现所谓的蔡氏电路的神经蜂窝网络，并且包括至少具有相应的第一和第二输入端子和相应状态端子的第一，第二和第三单元，所述第一和第二输入端子用于接收第一和第二参考信号和第一单元，第二和第三单元是相互不同的类型。

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