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11. 发明申请

US20130339573A1 OPTIMIZING WRITE PERFORMANCE TO FLASH MEMORY 审中-公开
标题翻译：优化写入闪存的写入性能
公开(公告)号：US20130339573A1
公开(公告)日：2013-12-19
申请号：US13524484
申请日：2012-06-15
申请人： Clark A. Anderson , Edward W. Chencinski , Jon S. Entwistle , Adrian C. Gerhard , Thomas J. Griffin , Charles E. Mari , Kenneth J. Oakes , Steven M. Partlow , Peter G. Sutton , Elpida Tzortzatos , Dustin J. VanStee
发明人： Clark A. Anderson , Edward W. Chencinski , Jon S. Entwistle , Adrian C. Gerhard , Thomas J. Griffin , Charles E. Mari , Kenneth J. Oakes , Steven M. Partlow , Peter G. Sutton , Elpida Tzortzatos , Dustin J. VanStee
IPC分类号： G06F12/02
CPC分类号： G06F12/08 , G06F2212/214
摘要： Embodiments relate to optimizing write performance of a flash device. Aspects include receiving a request to evict a plurality of pages from a main memory and determining a block size for the flash device. Aspects also include grouping the plurality of pages from the main memory into a move specification block, wherein a size of the move specification block is the block size and writing the move specification block to the flash device. The block size being determined based on one or more operational characteristics of the flash device.
摘要翻译：实施例涉及优化闪存设备的写入性能。方面包括接收从主存储器驱逐多个页面并确定闪存设备的块大小的请求。方面还包括将来自主存储器的多个页面分组为移动指定块，其中移动指定块的大小是块大小并将移动指定块写入闪存设备。块尺寸是基于闪光装置的一个或多个操作特性确定的。

12. 发明申请

US20130191700A1 BIT ERROR RATE BASED WEAR LEVELING FOR SOLID STATE DRIVE MEMORY 有权
标题翻译：用于固态驱动存储器的基于误码率的磨损等级
公开(公告)号：US20130191700A1
公开(公告)日：2013-07-25
申请号：US13355050
申请日：2012-01-20
申请人： Thomas J. Griffin , Dustin J. Vanstee
发明人： Thomas J. Griffin , Dustin J. Vanstee
IPC分类号： G06F11/16
CPC分类号： G01R31/3171 , G06F11/008 , G06F11/076 , G06F11/1048 , G06F11/1068 , G06F11/16 , G11C11/406 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3468 , G11C16/3495 , G11C29/42 , G11C29/50 , H04L1/203
摘要： According to exemplary embodiments, a system, method, and computer program product are provided for BER-based wear leveling in a SSD. A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.
摘要翻译：根据示例性实施例，提供了一种用于SSD中的基于BER的磨损均衡的系统，方法和计算机程序产品。确定SSD中的块的块级BER值。块的调整PE周期计数根据块级BER值递增或递减。然后，根据调整后的PE循环次数，在SSD中进行磨损均衡。

13. 发明申请

US20130151914A1 FLASH ARRAY BUILT IN SELF TEST ENGINE WITH TRACE ARRAY AND FLASH METRIC REPORTING 有权
标题翻译：闪存阵列用自动测试引擎内置跟踪阵列和闪存公制报告
公开(公告)号：US20130151914A1
公开(公告)日：2013-06-13
申请号：US13314657
申请日：2011-12-08
申请人： David D. Cadigan , Thomas J. Griffin , Archana Shetty , Gary A. Tressler , Dustin J. Vanstee
发明人： David D. Cadigan , Thomas J. Griffin , Archana Shetty , Gary A. Tressler , Dustin J. Vanstee
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G06F11/1068 , G11C16/00 , G11C29/16
摘要： A mechanism is provided for a flash array test engine. The flash array test engine includes a circuit. The circuit is configured to generate test workloads in a test mode for testing a flash device array, where each of the test workloads includes specific addresses, data, and command patterns to be sent to the flash device array. The circuit is configured to accelerate wear in the flash device array, via the test workloads, at an accelerated rate relative to general system workloads that are not part of the test mode. The circuit is configured to vary a range of conditions for the flash device array to determine whether each of the conditions passes or fails and to store failure data and corresponding failure data address information for the flash device array.
摘要翻译：为闪存阵列测试引擎提供了一种机制。闪存阵列测试引擎包括一个电路。电路被配置为在测试模式下生成测试工作负载，用于测试闪存器件阵列，其中每个测试工作负载包括要发送到闪存器件阵列的特定地址，数据和命令模式。该电路被配置为相对于不属于测试模式的一般系统工作负载，以加速的速度通过测试工作负载加速闪存器件阵列中的磨损。电路被配置为改变闪存器件阵列的条件范围，以确定每个条件是否通过或失败，并存储闪存器件阵列的故障数据和相应的故障数据地址信息。

14. 发明授权

US07979616B2 System and method for providing a configurable command sequence for a memory interface device 失效
标题翻译：为存储器接口设备提供可配置命令序列的系统和方法
公开(公告)号：US07979616B2
公开(公告)日：2011-07-12
申请号：US11767118
申请日：2007-06-22
申请人： Elianne A. Bravo , Kevin C. Gower , Dustin J. VanStee
发明人： Elianne A. Bravo , Kevin C. Gower , Dustin J. VanStee
IPC分类号： G06F13/00 , G06F3/00 , G06F5/00 , G06F11/00 , G06F12/00 , G06F13/28
CPC分类号： G06F13/1684
摘要： A system and method for providing a configurable command sequence for a memory interface device (MID). The system includes a MID intended for use in a cascade interconnect system and in communication with one or more memory devices. The MID includes a first connection to a high speed bus operating at a first data rate, a second connection to the high speed bus, an alternate communication means and logic. The first connection to the high speed bus includes receiver circuitry operating at the first data rate. The alternate communication means operates at a second data rate that is slower than the first data rate. The logic facilitates receiving commands via the first connection from the high speed bus operating at the first data rate and using a first command sequence. The logic also facilitates receiving the commands via the alternate communication means using a second command sequence which differs from the first command sequence in the speed in which the commands are transferred. The logic further facilitates processing the commands if the commands are directed to the MID and redriving the commands via the second connection onto the high speed bus.
摘要翻译：一种用于为存储器接口设备（MID）提供可配置命令序列的系统和方法。该系统包括MID，其用于级联互连系统并与一个或多个存储器件通信。 MID包括与以第一数据速率操作的高速总线的第一连接，到高速总线的第二连接，备用通信装置和逻辑。与高速总线的第一连接包括以第一数据速率工作的接收器电路。备用通信装置以比第一数据速率慢的第二数据速率工作。该逻辑有助于通过第一连接从第一数据速率的高速总线接收命令并使用第一命令序列。逻辑还通过使用与命令传送的速度不同的第一命令序列的第二命令序列，便于经由备用通信装置接收命令。如果命令指向MID并通过第二连接将命令重新转移到高速总线上，则该逻辑进一步有助于处理命令。

15. 发明授权

US07624225B2 System and method for providing synchronous dynamic random access memory (SDRAM) mode register shadowing in a memory system 失效
标题翻译：用于在存储器系统中提供同步动态随机存取存储器（SDRAM）模式寄存器阴影的系统和方法
公开(公告)号：US07624225B2
公开(公告)日：2009-11-24
申请号：US11689647
申请日：2007-03-22
申请人： Kevin C. Gower , Thomas J. Griffin , Kirk D. Lamb , Dustin J. VanStee
发明人： Kevin C. Gower , Thomas J. Griffin , Kirk D. Lamb , Dustin J. VanStee
IPC分类号： G06F12/00
CPC分类号： G11C7/1045 , G11C5/04 , G11C7/10 , G11C7/1003
摘要： A system and method for providing SDRAM mode register shadowing in a memory system. A system includes a memory interface device adapted for use in a memory system. The memory interface device includes an interface to one or more ranks of memory devices, and each memory device includes one or more types of mode registers. The memory interface device also includes an interface to a memory bus for receiving commands from a memory controller. The commands include a mode register set command specifying a new mode register setting for one or more ranks of memory devices and a mode register type. The memory interface device further includes a mode register shadow module to capture settings applied to the mode registers. The module includes a shadow register for each type of mode register and a shadow log for each type of mode register. The module also includes mode register shadow logic to detect a mode register set command, to store the new mode register setting in the shadow register corresponding to the specified mode register type, and to set one or more bits in the shadow log corresponding to the specified mode register type to indicate which of the ranks of memory devices have been programmed with the new mode register setting.
摘要翻译：一种用于在存储器系统中提供SDRAM模式寄存器阴影的系统和方法。系统包括适于在存储器系统中使用的存储器接口设备。存储器接口设备包括到一个或多个存储器设备等级的接口，并且每个存储器设备包括一种或多种类型的模式寄存器。存储器接口设备还包括到存储器总线的接口，用于从存储器控制器接收命令。这些命令包括指定用于一个或多个存储器件级别的模式寄存器设置的模式寄存器设置命令和模式寄存器类型。存储器接口设备还包括模式寄存器阴影模块，用于捕获应用于模式寄存器的设置。该模块包括每种类型的模式寄存器的影子寄存器和每种类型的模式寄存器的影子日志。该模块还包括模式寄存器阴影逻辑，用于检测模式寄存器设置命令，将新模式寄存器设置存储在与指定模式寄存器类型相对应的影子寄存器中，并设置与指定的对应的影子日志中的一个或多个位模式寄存器类型，以指示使用新模式寄存器设置来编程存储器件的哪些等级。

16. 发明授权

US09003068B2 Service channel for connecting a host computer to peripheral devices 有权
标题翻译：将主机连接到外围设备的服务通道
公开(公告)号：US09003068B2
公开(公告)日：2015-04-07
申请号：US13547369
申请日：2012-07-12
申请人： David D. Cadigan , Thomas J. Griffin , M. Dean Sciacca , Dustin J. VanStee
发明人： David D. Cadigan , Thomas J. Griffin , M. Dean Sciacca , Dustin J. VanStee
IPC分类号： G06F3/00 , G06F1/18
CPC分类号： G06F1/185
摘要： A computer system having a host adapter is provided. The host adapter includes a primary port that follows a primary communication protocol. The primary port is connectable to at least one peripheral device. The host adapter includes a service port that follows a service communication protocol to monitor and send recovery commands to the peripheral device. The service port is decoupled and separate from the primary port and connectable to the at least one peripheral device.
摘要翻译：提供具有主机适配器的计算机系统。主机适配器包括遵循主要通信协议的主端口。主端口可连接至少一个外围设备。主机适配器包括遵循服务通信协议的服务端口，以监视和发送恢复命令到外围设备。服务端口被解耦并与主端口分离并且可连接到至少一个外围设备。

17. 发明授权

US07606988B2 Systems and methods for providing a dynamic memory bank page policy 失效
标题翻译：用于提供动态记忆库页面策略的系统和方法
公开(公告)号：US07606988B2
公开(公告)日：2009-10-20
申请号：US11668093
申请日：2007-01-29
申请人： Kevin C. Gower , Dustin J. VanStee
发明人： Kevin C. Gower , Dustin J. VanStee
IPC分类号： G06F12/00
CPC分类号： G06F13/1694 , G06F12/0215 , G06F13/161 , G06F13/1684
摘要： Systems and methods for providing a dynamic memory buffer bank policy. Embodiments include a hub device for selecting a bank page policy. The hub device includes an input command stream interface and a bank page policy module. The input command stream interface detects commands from a memory controller that are directed to one or more memory devices that are connected to the hub device. The bank page policy module independently analyzes the commands to determine access patterns to the memory devices and for dynamically selecting between an open bank page policy and a closed bank page policy for the memory devices based on the analysis.
摘要翻译：提供动态内存缓冲区银行策略的系统和方法。实施例包括用于选择银行页面策略的集线器设备。集线器设备包括输入命令流接口和银行页策略模块。输入命令流接口检测来自存储器控制器的命令，其被定向到连接到集线器设备的一个或多个存储器设备。银行页面策略模块独立地分析用于确定对存储器设备的访问模式的命令，并且基于分析来动态地在存储设备的开放银行页面策略和封闭的银行页面策略之间进行选择。

18. 发明授权

US07603526B2 Systems and methods for providing dynamic memory pre-fetch 有权
标题翻译：提供动态内存预取的系统和方法
公开(公告)号：US07603526B2
公开(公告)日：2009-10-13
申请号：US11668088
申请日：2007-01-29
申请人： Dustin J. VanStee , Kevin C. Gower
发明人： Dustin J. VanStee , Kevin C. Gower
IPC分类号： G06F12/00
CPC分类号： G06F13/161
摘要： Systems and methods for providing dynamic memory pre-fetch. Embodiments include a hub device including an input command stream interface and an adaptive pre-fetch logical unit (APLU). The input command stream interface detects commands from a memory controller directed to one or more memory devices that are connected to the hub device. The APLU independently analyzes the commands to determine access patterns to the memory devices. The APLU also dynamically selects between enabling a pre-fetch function and disabling the pre-fetch function for the memory devices based on the results of the analysis.
摘要翻译：提供动态内存预取的系统和方法。实施例包括包括输入命令流接口和自适应预取逻辑单元（APLU）的集线器设备。输入命令流接口检测来自指向连接到集线器设备的一个或多个存储器设备的存储器控制器的命令。 APLU独立分析命令以确定存储器件的访问模式。 APLU还可以根据分析结果动态选择启用预取功能和禁用存储设备的预取功能。

19. 发明申请

US20080235444A1 SYSTEM AND METHOD FOR PROVIDING SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM) MODE REGISTER SHADOWING IN A MEMORY SYSTEM 失效
标题翻译：用于在存储器系统中提供同步动态随机存取存储器（SDRAM）模式寄存器的系统和方法
公开(公告)号：US20080235444A1
公开(公告)日：2008-09-25
申请号：US11689647
申请日：2007-03-22
申请人： Kevin C. Gower , Thomas J. Griffin , Kirk D. Lamb , Dustin J. VanStee
发明人： Kevin C. Gower , Thomas J. Griffin , Kirk D. Lamb , Dustin J. VanStee
IPC分类号： G06F12/00
CPC分类号： G11C7/1045 , G11C5/04 , G11C7/10 , G11C7/1003
摘要： A system and method for providing SDRAM mode register shadowing in a memory system. A system includes a memory interface device adapted for use in a memory system. The memory interface device includes an interface to one or more ranks of memory devices, and each memory device includes one or more types of mode registers. The memory interface device also includes an interface to a memory bus for receiving commands from a memory controller. The commands include a mode register set command specifying a new mode register setting for one or more ranks of memory devices and a mode register type. The memory interface device further includes a mode register shadow module to capture settings applied to the mode registers. The module includes a shadow register for each type of mode register and a shadow log for each type of mode register. The module also includes mode register shadow logic to detect a mode register set command, to store the new mode register setting in the shadow register corresponding to the specified mode register type, and to set one or more bits in the shadow log corresponding to the specified mode register type to indicate which of the ranks of memory devices have been programmed with the new mode register setting.
摘要翻译：一种用于在存储器系统中提供SDRAM模式寄存器阴影的系统和方法。系统包括适于在存储器系统中使用的存储器接口设备。存储器接口设备包括到一个或多个存储器设备等级的接口，并且每个存储器设备包括一种或多种类型的模式寄存器。存储器接口设备还包括到存储器总线的接口，用于从存储器控制器接收命令。这些命令包括指定用于一个或多个存储器件级别的模式寄存器设置的模式寄存器设置命令和模式寄存器类型。存储器接口设备还包括模式寄存器阴影模块，用于捕获应用于模式寄存器的设置。该模块包括每种类型的模式寄存器的影子寄存器和每种类型的模式寄存器的影子日志。该模块还包括模式寄存器阴影逻辑，用于检测模式寄存器设置命令，将新模式寄存器设置存储在与指定模式寄存器类型相对应的影子寄存器中，并设置与指定的对应的影子日志中的一个或多个位模式寄存器类型，以指示使用新模式寄存器设置来编程存储器件的哪些等级。

20. 发明申请

US20080115137A1 SYSTEMS AND METHODS FOR PROVIDING COLLISION DETECTION IN A MEMORY SYSTEM 有权
标题翻译：用于在记忆系统中提供碰撞检测的系统和方法
公开(公告)号：US20080115137A1
公开(公告)日：2008-05-15
申请号：US11461933
申请日：2006-08-02
申请人： Kevin C. Gower , Thomas J. Griffin , Dustin J. VanStee
发明人： Kevin C. Gower , Thomas J. Griffin , Dustin J. VanStee
IPC分类号： G06F9/46
CPC分类号： G06F13/4239 , G06F9/52
摘要： Systems and methods for providing collision detection in a memory system including a memory system for storing and retrieving data for a processing system. The memory system includes resource scheduling conflict logic for monitoring one or more memory resources for detecting resource scheduling conflicts. The memory system also includes error reporting logic for generating an error signal in response to detecting a resource scheduling conflict at one or more of the memory resources.
摘要翻译：用于在包括用于存储和检索用于处理系统的数据的存储器系统的存储器系统中提供冲突检测的系统和方法。存储器系统包括用于监视用于检测资源调度冲突的一个或多个存储器资源的资源调度冲突逻辑。存储器系统还包括用于响应于检测到一个或多个存储器资源上的资源调度冲突而产生错误信号的错误报告逻辑。

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