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11. 发明申请

US20070009840A1 Method of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070009840A1
公开(公告)日：2007-01-11
申请号：US11480545
申请日：2006-07-05
申请人： Dong-chan Kim , Chang-jin Kang , Kyeong-koo Chi
发明人： Dong-chan Kim , Chang-jin Kang , Kyeong-koo Chi
IPC分类号： G03F7/26
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/76816 , H01L21/76897 , Y10S438/947
摘要： A method of fabricating a semiconductor device comprising a method of forming an etching mask used for etching a semiconductor base material is disclosed. The method of fabricating a semiconductor device comprises forming hard mask patterns on a semiconductor base material; forming material layers covering the lateral and top surfaces of the hard mask patterns to form openings between adjacent hard mask patterns, wherein the width of each opening is smaller than the distance between adjacent hard mask patterns; and etching the semiconductor base material using the hard mask patterns and material layers as an etching mask.
摘要翻译：公开了一种制造半导体器件的方法，包括形成用于蚀刻半导体基底材料的蚀刻掩模的方法。制造半导体器件的方法包括在半导体基底材料上形成硬掩模图案; 形成覆盖硬掩模图案的侧表面和顶表面的材料层，以在相邻的硬掩模图案之间形成开口，其中每个开口的宽度小于相邻硬掩模图案之间的距离; 并使用硬掩模图案和材料层作为蚀刻掩模蚀刻半导体基底材料。

12. 发明申请

US20060231822A1 Flash memory devices and methods of fabricating the same 有权
公开(公告)号：US20060231822A1
公开(公告)日：2006-10-19
申请号：US11358897
申请日：2006-02-21
申请人： Dong-Chan Kim
发明人： Dong-Chan Kim
IPC分类号： H01L47/00
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A flash memory device includes a common source region that is disposed in an active region at a side of a ground-selection gate line, being apart from the ground-selection gate line. A pair of source spacers crosses over both top edges of the common source region. A source line fills up a space between the pair of source spacers. The top surface of the source line is equal to or lower than the that of the ground-selection gate line.

13. 发明授权

US09916900B2 Memory device, memory system, method of operating memory device, and method of operating memory system 有权
公开(公告)号：US09916900B2
公开(公告)日：2018-03-13
申请号：US15245162
申请日：2016-08-23
申请人： Yoon Kim , Dong-chan Kim , Ji-sang Lee
发明人： Yoon Kim , Dong-chan Kim , Ji-sang Lee
IPC分类号： G11C11/56 , G11C16/14 , G11C16/34 , G11C16/10 , G11C16/04
CPC分类号： G11C16/14 , G11C11/5635 , G11C16/0483 , G11C16/107 , G11C16/349
摘要： A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.

14. 发明申请

US20140138639A1 ORGANIC LIGHT EMITTING DIODE AND ORGANIC LIGHT EMITTING DIODE DISPLAY 有权
标题翻译：有机发光二极管和有机发光二极管显示
公开(公告)号：US20140138639A1
公开(公告)日：2014-05-22
申请号：US13900845
申请日：2013-05-23
申请人： Dong-Chan KIM , Jong-Hyuk LEE , Young-Woo SONG , Won-Jong KIM , Kyu-Hwan HWANG , Seok-Gyu YOON , Eung-Do KIM , Bo-Ra JUNG , Dong-Kyu SEO
发明人： Dong-Chan KIM , Jong-Hyuk LEE , Young-Woo SONG , Won-Jong KIM , Kyu-Hwan HWANG , Seok-Gyu YOON , Eung-Do KIM , Bo-Ra JUNG , Dong-Kyu SEO
IPC分类号： H01L51/52
CPC分类号： H01L51/5218 , H01L2251/5315
摘要： An organic light emitting diode includes a first electrode including a reflective metal layer of a light-reflective metal, an upper transparent conductive layer on the reflective metal layer, and an amorphous oxide layer on the upper transparent conductive layer, an organic emission layer on the first electrode, and a second electrode on the organic emission layer.
摘要翻译：有机发光二极管包括：第一电极，其包括反射金属层的反射金属层，反射金属层上的上部透明导电层和上部透明导电层上的无定形氧化物层; 第一电极和有机发射层上的第二电极。

15. 发明申请

US20140134812A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20140134812A1
公开(公告)日：2014-05-15
申请号：US14060806
申请日：2013-10-23
申请人： Dong-Chan KIM , Tai-Su PARK , Ju-Eun KIM , Ki-Hong NAM
发明人： Dong-Chan KIM , Tai-Su PARK , Ju-Eun KIM , Ki-Hong NAM
IPC分类号： H01L29/66 , H01L21/28 , H01L21/283 , H01L29/78 , H01L21/324
CPC分类号： H01L21/28185 , H01L21/02164 , H01L21/0228 , H01L21/28194 , H01L27/10814 , H01L27/10876 , H01L27/10888 , H01L29/513 , H01L29/517
摘要： A method of fabricating a semiconductor device includes forming a trench in a substrate, forming a pre-gate insulating film along side surfaces and a bottom surface of the trench, and oxidizing the pre-gate insulating film through a densification process.
摘要翻译：制造半导体器件的方法包括在衬底中形成沟槽，沿着沟槽的侧表面和底表面形成预栅绝缘膜，并通过致密化过程来氧化预栅绝缘膜。

16. 发明申请

US20120282769A1 METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING ELECTRICALLY CONDUCTIVE LAYERS THEREIN WITH PARTIALLY NITRIDATED SIDEWALLS 有权
标题翻译：形成具有部分硝化面的电导体层的集成电路装置的方法
公开(公告)号：US20120282769A1
公开(公告)日：2012-11-08
申请号：US13551251
申请日：2012-07-17
申请人： Jeong-Do Ryu , Si-Young CHOI , Yu-Gyun SHIN , Tai-Su PARK , Dong-Chan KIM , Jong-Ryeol YOO , Seong-Hoon JEONG , Jong-Hoon KANG
发明人： Jeong-Do Ryu , Si-Young CHOI , Yu-Gyun SHIN , Tai-Su PARK , Dong-Chan KIM , Jong-Ryeol YOO , Seong-Hoon JEONG , Jong-Hoon KANG
IPC分类号： H01L21/28
CPC分类号： H01L21/28061 , H01L21/28247 , H01L21/3211 , H01L21/32137 , H01L21/32139 , H01L27/10873 , H01L27/11 , H01L27/1104
摘要： Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.
摘要翻译：形成集成电路器件的方法包括在衬底上形成含硅的导电层，并在导电层上形成掩模图案。使用掩模图案作为蚀刻掩模，选择性地蚀刻导电层以限定其上的第一侧壁。可以将导电层的第一侧壁暴露于氮等离子体，从而在第一侧壁上形成第一氮化硅层。然后再次选择性地蚀刻导电层以暴露其上没有第一氮化硅层的第二侧壁。在选择性蚀刻导电层的第二步骤期间，掩模图案可以再次用作蚀刻掩模。

17. 发明申请

US20110049467A1 Manufacturing method of metal oxide nanostructure and electronic element having the same 有权
标题翻译：金属氧化物纳米结构的制造方法和具有该金属氧化物纳米结构的电子元件
公开(公告)号：US20110049467A1
公开(公告)日：2011-03-03
申请号：US12862895
申请日：2010-08-25
申请人： Hyung Koun Cho , Dong Chan Kim
发明人： Hyung Koun Cho , Dong Chan Kim
IPC分类号： H01L29/66 , H01L21/34
CPC分类号： H01L21/0262 , B82Y10/00 , H01L21/0237 , H01L21/02472 , H01L21/02483 , H01L21/02554 , H01L21/02565 , H01L21/02603 , H01L21/02645 , H01L29/0665 , H01L29/0676 , Y10S977/811 , Y10S977/89
摘要： Disclosed herein is a manufacturing method of metal oxide nanostructure, including the steps of: (S1) supplying a precursor containing a first metal, a precursor containing a second metal and oxygen onto a substrate; (S2) forming an amorphous second metal oxide layer on the substrate; (S3) forming first nuclei containing the first metal as a main component and second nuclei containing the second metal as a main component on the substrate; (S4) converting the first nuclei into single crystalline seed layers spaced apart from each other and converting the second nuclei into amorphous layers surrounding the first nuclei; and (S5) selectively forming rods on the seed layers and then growing the rods.The manufacturing method of metal oxide nanostructure is advantageous in that the area and thickness of an amorphous layer can be controlled by controlling the flow rate of the main component of the amorphous layer and the flow rate of the main component of the single crystalline seed layer, thereby controlling the density and diameter of the seed layer.
摘要翻译：本文公开了一种金属氧化物纳米结构的制造方法，包括以下步骤：（S1）将含有第一金属的前体和含有第二金属和氧的前体供给到基板上; （S2），在所述基板上形成非晶质的第二金属氧化物层; （S3）在所述基板上形成以所述第一金属为主要成分的第一核和包含所述第二金属作为主要成分的第二核; （S4）将第一核转换成彼此间隔开的单晶种子层，并将第二核转变成围绕第一核的非晶层; 和（S5）选择性地在种子层上形成棒，然后使棒生长。金属氧化物纳米结构的制造方法的优点在于，可以通过控制非晶层的主成分的流量和单晶种子层的主成分的流量来控制非晶层的面积和厚度，从而控制种子层的密度和直径。

18. 发明授权

US07709389B2 Method of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07709389B2
公开(公告)日：2010-05-04
申请号：US11480545
申请日：2006-07-05
申请人： Dong-chan Kim , Chang-jin Kang , Kyeong-koo Chi
发明人： Dong-chan Kim , Chang-jin Kang , Kyeong-koo Chi
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/76816 , H01L21/76897 , Y10S438/947
摘要： A method of fabricating a semiconductor device comprising a method of forming an etching mask used for etching a semiconductor base material is disclosed. The method of fabricating a semiconductor device comprises forming hard mask patterns on a semiconductor base material; forming material layers covering the lateral and top surfaces of the hard mask patterns to form openings between adjacent hard mask patterns, wherein the width of each opening is smaller than the distance between adjacent hard mask patterns; and etching the semiconductor base material using the hard mask patterns and material layers as an etching mask.
摘要翻译：公开了一种制造半导体器件的方法，包括形成用于蚀刻半导体基底材料的蚀刻掩模的方法。制造半导体器件的方法包括在半导体基底材料上形成硬掩模图案; 形成覆盖硬掩模图案的侧表面和顶表面的材料层，以在相邻的硬掩模图案之间形成开口，其中每个开口的宽度小于相邻硬掩模图案之间的距离; 并使用硬掩模图案和材料层作为蚀刻掩模蚀刻半导体基底材料。

19. 发明申请

US20100072545A1 Recessed Channel Array Transistors, and Semiconductor Devices Including a Recessed Channel Array Transistor 有权
标题翻译：嵌入式通道阵列晶体管和包括嵌入式通道阵列晶体管的半导体器件
公开(公告)号：US20100072545A1
公开(公告)日：2010-03-25
申请号：US12563473
申请日：2009-09-21
申请人： Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
发明人： Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
IPC分类号： H01L27/06 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/28211 , H01L21/823412 , H01L27/105 , H01L27/10876 , H01L27/10879 , H01L27/10894 , H01L27/11 , H01L29/4236 , H01L29/51 , H01L29/66621 , H01L29/7851
摘要： A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.
摘要翻译：凹陷通道阵列晶体管可以包括衬底，栅极氧化物层，栅极电极和源极/漏极区域。衬底可以具有有源区和隔离区。可以在活性区域中形成凹陷。栅极氧化物层可以形成在凹部和基板上。栅极氧化物层可以包括在凹部的侧端和有源区的侧壁与凹部的侧表面上的第二部分之间的交叉处的第一部分。第一部分可以包括大于第二部分厚度的约70％的厚度。栅极电极可以形成在栅极氧化物层上。源极/漏极区域可以形成在衬底中。因此，凹陷通道阵列晶体管可能具有减小的漏电流和增加的导通电流。

20. 发明授权

US07618899B2 Method of patterning a matrix into a substrate via multiple, line-and-space, sacrificial, hard mask layers 有权
标题翻译：通过多个线，空间，牺牲的硬掩模层将基体图案化成衬底的方法
公开(公告)号：US07618899B2
公开(公告)日：2009-11-17
申请号：US11847223
申请日：2007-08-29
申请人： Seung-Pil Chung , Dong-Chan Kim , Chang-Jin Kang , Heung-Sik Park
发明人： Seung-Pil Chung , Dong-Chan Kim , Chang-Jin Kang , Heung-Sik Park
IPC分类号： H01L21/31 , H01L21/308
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/3081 , H01L21/3086
摘要： Methods of fabricating a semiconductor integrated circuit device are disclosed. The methods of fabricating a semiconductor integrated circuit device include forming a hard mask layer on a base layer, forming a line sacrificial hard mask layer on the hard mask layer in a first direction, coating a high molecular organic material layer on the line sacrificial hard mask layer pattern, patterning the high molecular organic material layer and the line sacrificial hard mask layer pattern in a second direction, forming a matrix sacrificial hard mask layer pattern, forming a hard mask layer pattern by patterning the hard mask layer with the matrix sacrificial hard mask layer pattern as an etching mask and forming a lower pattern by patterning the base layer using the hard mask layer pattern as an etch mask. The method according to the invention is simpler and less expensive than conventional methods.
摘要翻译：公开了制造半导体集成电路器件的方法。制造半导体集成电路器件的方法包括在基底层上形成硬掩模层，在第一方向上在硬掩模层上形成线牺牲硬掩模层，在牺牲硬掩模上涂覆高分子有机材料层层状图案，在第二方向上图案化高分子有机材料层和线牺牲硬掩模层图案，形成矩阵牺牲硬掩模层图案，通过用基体牺牲硬掩模图案化硬掩模层形成硬掩模层图案层图案作为蚀刻掩模，并且通过使用硬掩模层图案作为蚀刻掩模对基底层进行图案化来形成下图案。根据本发明的方法比常规方法更简单和便宜。

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