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11. 发明授权

US5638201A Optically active diffractive device 失效
$Optically active diffractive device$
标题翻译：光学活性衍射装置
公开(公告)号：US5638201A
公开(公告)日：1997-06-10
申请号：US445051
申请日：1995-05-19
申请人： Philip J. Bos , David L. Johnson , Jianmin Chen , Hemasiri K. Vithana , William E. Glenn , Carvel E. Holton , Brett E. Smith
发明人： Philip J. Bos , David L. Johnson , Jianmin Chen , Hemasiri K. Vithana , William E. Glenn , Carvel E. Holton , Brett E. Smith
IPC分类号： G02F1/1337 , G02F1/139 , G02F1/29
CPC分类号： G02F1/133753 , G02F1/1396 , G02F1/292 , G02F2201/305 , G02F2203/48
摘要： A liquid crystalline diffractive light valve for use in a diffractive projection system. The liquid crystal cell includes substrates treated to provide alternating stripes which cooperate with the liquid crystal to form liquid crystal domains extending across the thickness of the cell that will produce a 180.degree. phase difference in light emerging from adjacent domains, irrespective of the polarization of incident light.
摘要翻译：一种用于衍射投影系统的液晶衍射光阀。液晶单元包括处理以提供与液晶配合的交替条纹的基板，以形成跨越单元的厚度延伸的液晶畴，其将从相邻畴产生的光产生180°的相位差，而与事件的极化无关光。

12. 发明授权

US07868599B2 Method of optimum current blanking time implementation in current sense circuit 有权
标题翻译：电流检测电路实现最佳电流消隐时间的方法
公开(公告)号：US07868599B2
公开(公告)日：2011-01-11
申请号：US11986775
申请日：2007-11-26
申请人： Md Abidur Rahman , Huijuan Li , Brett E. Smith , Zheng Li
发明人： Md Abidur Rahman , Huijuan Li , Brett E. Smith , Zheng Li
IPC分类号： G05F1/00
CPC分类号： G01R19/0092 , H02M3/158 , H02M2001/0009
摘要： In a method and system for sensing current in a switching regulator (SWR) operating in a current mode, a power switch is coupled to receive the current from a switching element, the power switch being controlled by a gate signal. An inrush of the current causes an initial transient spike (ITS). A buffer having a buffer input and a buffer output is coupled to receive the gate signal and provide a buffered gate signal. The buffer output is disabled during the ITS. A sense switch (SW) is coupled to receive a portion of the current from the switching element, the SW being turned on by the buffered gate signal after the initial transient spike. A sense resistor (SR) is coupled to receive the portion of the current from the SW. An amplifier converts the portion of the current through the SR to a voltage signal for controlling the SWR.
摘要翻译：在用于感测以当前模式工作的开关调节器（SWR）中的电流的方法和系统中，电源开关被耦合以从开关元件接收电流，功率开关由门信号控制。电流的浪涌导致初始瞬态尖峰（ITS）。具有缓冲器输入和缓冲器输出的缓冲器被耦合以接收栅极信号并提供缓冲的栅极信号。缓冲区输出在ITS期间被禁用。感测开关（SW）被耦合以从开关元件接收电流的一部分，在初始瞬态尖峰之后，SW被缓冲的栅极信号导通。耦合感测电阻器（SR）以从SW接收电流的一部分。放大器将通过SR的电流的一部分转换成用于控制SWR的电压信号。

13. 发明申请

US20070278994A1 SYSTEMS AND METHODS FOR MULTI-MODE BATTERY CHARGING 有权
标题翻译：多模式电池充电的系统和方法
公开(公告)号：US20070278994A1
公开(公告)日：2007-12-06
申请号：US11748008
申请日：2007-05-14
申请人： Valerian Mayega , Percy E. Neyra , Brett E. Smith
发明人： Valerian Mayega , Percy E. Neyra , Brett E. Smith
IPC分类号： H02J7/00
CPC分类号： H02J7/0072 , H02M3/156
摘要： Various systems and methods for battery charging are disclosed herein. As just one example, a battery charger is disclosed that includes a current feedback loop that has a pulse width modulated current control output, and a voltage feedback loop that has a pulse width modulated voltage control output. In addition, the battery charger includes a transition circuit with a digital phase/frequency detector. The digital phase/frequency detector is operable to detect a duty cycle difference between the pulse width modulated current control output and the pulse width modulated voltage control output. Further, the transition circuit is operable to transition between application of a substantially current charge control to a charging node to application of a substantially constant voltage to the charging node based at least in part on the difference in duty cycle.
摘要翻译：本文公开了用于电池充电的各种系统和方法。作为仅一个示例，公开了一种电池充电器，其包括具有脉宽调制电流控制输出的电流反馈回路和具有脉宽调制电压控制输出的电压反馈回路。此外，电池充电器包括具有数字相位/频率检测器的转换电路。数字相位/频率检测器可操作以检测脉宽调制电流控制输出和脉宽调制电压控制输出之间的占空比差异。此外，转换电路可操作以至少部分地基于占空比的差异，在施加基本上当前的充电控制到充电节点之间转换到向充电节点施加基本上恒定的电压。

14. 发明授权

US06952120B2 Versatile system for controlling driver signal timing 有权
标题翻译：用于控制驱动器信号时序的多功能系统
公开(公告)号：US06952120B2
公开(公告)日：2005-10-04
申请号：US10777991
申请日：2004-02-12
申请人： MD Abidur Rahman , William E. Grose , Brett E. Smith
发明人： MD Abidur Rahman , William E. Grose , Brett E. Smith
IPC分类号： H03B1/00 , H03K17/0412
CPC分类号： H03K17/04123
摘要： The present invention provides a system (200) for controlling drive signal timing parameters of an output driver circuit (206). The present invention defines a driver circuit having an output interface (204), and a first transistor (222) coupled to a first voltage supply (230), a first control signal (232), and a first node (220). The circuit also has a first resistive element, coupled between the first node and a second node (234). A second resistive element (228) is coupled to ground. A second transistor (224) is coupled to the second node, to a second control signal (236), and the second resistive element. The circuit has a third transistor (244), coupled to the first and second nodes, and to a third node (240). A third resistive element (242) is coupled between the third node and the output interface. A fourth transistor (238) is coupled to the first and third nodes, and to the output interface. The circuit also has a fifth transistor (216), coupled to a second voltage supply (218), to the first node, and to the output interface.
摘要翻译：本发明提供一种用于控制输出驱动电路（206）的驱动信号定时参数的系统（200）。本发明定义了具有输出接口（204）和耦合到第一电压源（230），第一控制信号（232）和第一节点（220）的第一晶体管（222）的驱动器电路。电路还具有耦合在第一节点和第二节点（234）之间的第一电阻元件。第二电阻元件（228）耦合到地。第二晶体管（224）耦合到第二节点，耦合到第二控制信号（236）和第二电阻元件。电路具有耦合到第一和第二节点以及耦合到第三节点（240）的第三晶体管（244）。第三电阻元件（242）耦合在第三节点和输出接口之间。第四晶体管（238）耦合到第一和第三节点以及输出接口。电路还具有耦合到第二电压源（218）的第五晶体管（216）到第一节点和输出接口。

15. 发明授权

US06719387B2 Method for reducing turn-off propagation delay in print head drivers 有权
公开(公告)号：US06719387B2
公开(公告)日：2004-04-13
申请号：US10200718
申请日：2002-07-22
申请人： Md Abidur Rahman , Brett E. Smith
发明人： Md Abidur Rahman , Brett E. Smith
IPC分类号： B41J2938
CPC分类号： B41J29/38
摘要： An improved inkjet print head driver. The driver includes a source of predrive charge for a first, drive transistor coupled by its source and drain between an output node and a power supply, and having its gate coupled to the source of predrive charge. A second transistor is provided, adapted to receive an input signal at its gate. A third, control transistor is coupled by its source and drain between the gate of the first transistor and the second transistor, the second transistor being coupled by its source and drain between the third transistor and ground. Optionally, a resistor is coupled in parallel with the third transistor, i.e., across the source and drain of the third transistor.

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