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11. 发明授权

US08687521B1 Avoiding mesh path discovery in wireless mesh networks 有权
标题翻译：在无线网状网络中避免网格路径发现
公开(公告)号：US08687521B1
公开(公告)日：2014-04-01
申请号：US13346177
申请日：2012-01-09
申请人： Sandesh Goel , Ashish Kumar Shukla
发明人： Sandesh Goel , Ashish Kumar Shukla
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04W40/246 , H04L45/122 , H04W40/12
摘要： A network interface of a first mesh point device, the network interface including a memory and a medium access controller. In response to the first mesh point device receiving a frame, the medium access controller determines whether a mesh path for routing the frame from the first mesh point device to a second mesh point device is stored in the memory. In response to a mesh path not being stored in the memory, and prior to performing a mesh path discovery protocol, the medium access controller (i) determines whether the second mesh point device is one hop from the first mesh point device, and if so selects a one hop path for routing the frame to the second mesh point device, otherwise (ii) uses the mesh path discovery protocol to determine a mesh path for routing the frame to the second mesh point device.
摘要翻译：第一网格点设备的网络接口，网络接口包括存储器和介质访问控制器。响应于第一网格点设备接收帧，介质访问控制器确定用于将帧从第一网格点设备路由到第二网格点设备的网格路径是否存储在存储器中。响应于不存储在存储器中的网格路径，并且在执行网格路径发现协议之前，介质访问控制器（i）确定第二网格点设备是否是来自第一网格点设备的一跳，并且如果是选择用于将帧路由到第二网格点设备的一跳路径，否则（ii）使用网格路径发现协议来确定用于将帧路由到第二网格点设备的网格路径。

12. 发明申请

US20120186980A1 METHODS AND SYSTEMS FOR SEPARATING IONS FROM FLUIDS 审中-公开
标题翻译：从流体中分离离子的方法和系统
公开(公告)号：US20120186980A1
公开(公告)日：2012-07-26
申请号：US13014496
申请日：2011-01-26
申请人： Sundara Ramaprabhu , Ashish Kumar Mishra
发明人： Sundara Ramaprabhu , Ashish Kumar Mishra
IPC分类号： B03C5/02 , B03C9/00 , C02F1/48 , B05D5/12 , B82Y30/00 , B82Y99/00
CPC分类号： C02F1/4691 , B03C5/02 , B03C2201/18 , B82Y30/00 , B82Y40/00 , C02F1/002 , C02F1/46114 , C02F2001/46138 , C02F2101/103 , C02F2103/06 , C02F2103/08 , C02F2201/46135 , C02F2201/4617 , C02F2305/08
摘要： Technologies are generally described for method and apparatus for separating ions, such as arsenic, from a fluid, such as water. The apparatus includes a capacitor. The capacitor includes a material having a nanoscale porous structure, such as a plurality of multi-walled carbon nanotubes (MWNTs), and metal oxide nanoparticles, such as magnetite, disposed over the nanoscale porous structure. A portable water purifier employing the capacitor can effectively remove ions from water with a low voltage applied to the capacitor.
摘要翻译：通常描述用于从流体（例如水）中分离离子（例如砷）的方法和装置的技术。该装置包括电容器。电容器包括具有纳米级多孔结构的材料，例如多个多壁碳纳米管（MWNT），以及设置在纳米尺度多孔结构上的诸如磁铁矿的金属氧化物纳米颗粒。使用电容器的便携式净水器可以以低电压施加到电容器上，有效地从水中去除离子。

13. 发明授权

US08149715B1 Mesh network operations 有权
标题翻译：网状网络操作
公开(公告)号：US08149715B1
公开(公告)日：2012-04-03
申请号：US12167841
申请日：2008-07-03
申请人： Sandesh Goel , Ashish Kumar Shukla
发明人： Sandesh Goel , Ashish Kumar Shukla
IPC分类号： H04L1/00
CPC分类号： H04W52/0216 , H04L45/123 , H04W24/08 , H04W28/06 , H04W28/08 , H04W28/16 , H04W28/18 , H04W40/08 , H04W40/248 , Y02D70/142 , Y02D70/22 , Y02D70/23 , Y02D70/324
摘要： Various embodiments provide improved mesh networks with properties that address various shortcomings of current mesh network implementations. At least some embodiments are directed to improving operations of mesh networks in connection with battery powered devices and address concerns associated with latency issues due to power save nodes as well as load balancing. Yet other embodiments address route cache timeouts, reduce route discovery overhead, perform proactive route maintenance based on a node's battery, and provide a straightforward battery-aware process based sleep protocol.
摘要翻译：各种实施例提供具有解决当前网状网络实现的各种缺点的特性的改进的网状网络。至少一些实施例涉及改善与电池供电的设备相关的网状网络的操作以及由于节电节点以及负载平衡而与延迟问题相关联的地址问题。其他实施例解决了路由高速缓存超时，减少路由发现开销，基于节点的电池执行主动路由维护，并且提供基于电池感知的基于过程的简单的睡眠协议。

14. 再颁专利

USRE43081E1 Method and device for configuration of PLDS 有权
标题翻译： PLDS配置方法和设备
公开(公告)号：USRE43081E1
公开(公告)日：2012-01-10
申请号：US12136712
申请日：2008-06-10
申请人： Ashish Kumar Goel , Davinder Aggarwal
发明人： Ashish Kumar Goel , Davinder Aggarwal
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , G06F17/5054 , H03K19/1776
摘要： A Programmable Logic Device provides efficient scalability for configuration memory programming while requiring reduced area for implementation. The device includes an array of configuration memory cells, a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells, a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells, a Horizontal Shift Register (HSR) providing the enable input to the Select Register (SR), and a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR.
摘要翻译：可编程逻辑器件为配置存储器编程提供了有效的可扩展性，同时需要减少实现的面积。该装置包括配置存储器单元的阵列，连接到配置存储单元阵列的垂直线的垂直移位寄存器（VSR），连接到配置存储器单元阵列的水平线的选择寄存器（SR），提供给选择寄存器（SR）的使能输入的水平移位寄存器（HSR）和与VSR，SR和HSR的操作同步的配置状态机（CSM）。

15. 发明授权

US08094637B1 Avoiding mesh path discovery in wireless mesh networks 有权
标题翻译：在无线网状网络中避免网格路径发现
公开(公告)号：US08094637B1
公开(公告)日：2012-01-10
申请号：US12464958
申请日：2009-05-13
申请人： Sandesh Goel , Ashish Kumar Shukla
发明人： Sandesh Goel , Ashish Kumar Shukla
IPC分类号： H04W40/00 , H04W52/24 , H04L12/28
CPC分类号： H04W40/246 , H04L45/122 , H04W40/12
摘要： Apparatus having corresponding methods comprise: a mesh path module adapted to select a mesh path between a first mesh point in a mesh network and a second mesh point in the mesh network, wherein the mesh path module comprises a neighbor discovery module adapted to determine whether the second mesh point is one hop from the first mesh point, a one-hop mesh path module adapted to select a one-hop mesh path between the first mesh point and the second mesh point when the second mesh point is one hop from the first mesh point, and a multi-hop mesh path module adapted to discover a multi-hop mesh path between the first mesh point and the second mesh point only when it is determined that the second mesh point is not one hop from the first mesh point.
摘要翻译：具有相应方法的装置包括：网格路径模块，其适于在网状网络中的第一网格点和网状网络中的第二网格点之间选择网格路径，其中网状路径模块包括邻居发现模块，其适于确定是否第二网格点是从第一网格点开始一跳，当第二网格点距离第一网格是一跳时，适合于选择第一网格点和第二网格点之间的单跳网格路径的单跳网格路径模块以及多跳网格路径模块，其适于仅在确定所述第二网格点不是来自所述第一网格点的一跳时，发现所述第一网格点和所述第二网格点之间的多跳网格路径。

16. 发明申请

US20110026309A1 SELF-TIMED WRITE BOOST FOR SRAM CELL WITH SELF MODE CONTROL 有权
标题翻译：用于具有自我模式控制的SRAM单元的自定时写入
公开(公告)号：US20110026309A1
公开(公告)日：2011-02-03
申请号：US12571170
申请日：2009-09-30
申请人： Ashish KUMAR , Naveen Batra
发明人： Ashish KUMAR , Naveen Batra
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C11/413 , G11C5/145
摘要： A write boost circuit provides an automatic mode control for boost with different modalities with respect to the external supply voltage and also with respect to the extent of boost required at different process corners. The write boost circuit also takes care of the minimum boost provided to process corners with good writability where less boost is required. The boost is realized in terms of ground raising in the particular context and in general applicable to all other methods.
摘要翻译：写升压电路提供了一种自动模式控制，用于相对于外部电源电压的不同模式的升压，以及相对于不同工艺角所需的升压程度。写升压电路还负责处理拐角的最小提升，具有良好的写入性，需要较少的提升。在特定情况下，通过地面提升实现提升，一般适用于所有其他方法。

17. 发明授权

US07774682B2 Processing configuration data frames 有权
标题翻译：处理配置数据帧
公开(公告)号：US07774682B2
公开(公告)日：2010-08-10
申请号：US12032448
申请日：2008-02-15
申请人： Ashish Kumar Goel , Namerita Khanna , Davinder Aggarwal
发明人： Ashish Kumar Goel , Namerita Khanna , Davinder Aggarwal
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G06F11/1402 , G01R31/318519 , G06F11/1008
摘要： In at least some embodiments, a Programmable Logic Device (PLD) is configured to using a counter in conjunction with a threshold value to determine whether a configuration data frame is to be reloaded into a frame register if errors are encountered. In at least other embodiments, a Programmable Logic Device (PLD) is configured to sequentially load configuration data frames into a frame register, check for errors in the configuration data frames during sequentially loading, and correct errors during sequentially loading without reloading one or more previously-loaded different configuration data frames.
摘要翻译：在至少一些实施例中，可编程逻辑设备（PLD）被配置为结合阈值使用计数器，以确定如果遇到错误，配置数据帧是否被重新加载到帧寄存器中。在至少其他实施例中，可编程逻辑器件（PLD）被配置为将配置数据帧顺序地加载到帧寄存器中，在顺序加载期间检查配置数据帧中的错误，并且在顺序加载期间校正错误，而不重新加载一个或多个先前加载不同的配置数据帧。

18. 发明授权

US07606969B2 Programmable logic devices 有权
标题翻译：可编程逻辑器件
公开(公告)号：US07606969B2
公开(公告)日：2009-10-20
申请号：US11005247
申请日：2004-12-06
申请人： Davinder Aggarwal , Ashish Kumar Goel , Namerita Khanna
发明人： Davinder Aggarwal , Ashish Kumar Goel , Namerita Khanna
IPC分类号： G06F13/00
CPC分类号： H03K19/17748 , H03K19/1776
摘要： An improved programmable logic device provides increased efficiency and enhanced flexibility in configuration of block memories and includes one or more memory blocks and a vertical shift register that receives the data to be loaded in the memory blocks. The PLD further provides a selection device for selecting the memory cells in the memory blocks that are to store the received data, and a control block for controlling the loading of the data in the memory blocks. The selection device includes an address counter connected to the input of an address decoder so as to enable the selection of addresses in the memory blocks.
摘要翻译：改进的可编程逻辑器件在块存储器的配置中提供增加的效率和增强的灵活性，并且包括一个或多个存储器块和接收待加载到存储器块中的数据的垂直移位寄存器。 PLD还提供用于选择要存储接收到的数据的存储器块中的存储器单元的选择装置，以及用于控制数据在存储块中的加载的控制块。选择装置包括与地址解码器的输入连接的地址计数器，以便能够选择存储块中的地址。

19. 发明授权

US07293036B2 Compressing database workloads 有权
标题翻译：压缩数据库工作负载
公开(公告)号：US07293036B2
公开(公告)日：2007-11-06
申请号：US11008335
申请日：2004-12-08
申请人： Surajit Chaudhuri , Ashish Kumar Gupta , Vivek Narasayya
发明人： Surajit Chaudhuri , Ashish Kumar Gupta , Vivek Narasayya
IPC分类号： G06F17/30
CPC分类号： G06F17/30536 , G06F17/30306 , G06F17/30312 , Y10S706/917 , Y10S707/99932 , Y10S707/99942 , Y10S707/99945
摘要： Relational database applications such as index selection, histogram tuning, approximate query processing, and statistics selection have recognized the importance of leveraging workloads. Often these applications are presented with large workloads, i.e., a set of SQL DML statements, as input. A key factor affecting the scalability of such applications is the size of the workload. The invention concerns workload compression which helps improve the scalability of such applications. The exemplary embodiment is broadly applicable to a variety of workload-driven applications, while allowing for incorporation of application specific knowledge. The process is described in detail in the context of two workload-driven applications: index selection and approximate query processing.
摘要翻译：诸如索引选择，直方图调整，近似查询处理和统计选择等关系数据库应用程序已经认识到利用工作负载的重要性。通常，这些应用程序具有大的工作负载，即一组SQL DML语句作为输入。影响这些应用程序可扩展性的关键因素是工作负载的大小。本发明涉及工作负载压缩，这有助于提高这种应用的可扩展性。该示例性实施例广泛地适用于各种工作负载驱动的应用，同时允许结合应用特定的知识。该过程在两个工作负载驱动的应用程序的上下文中进行了详细描述：索引选择和近似查询处理。

20. 发明申请

US20060203536A1 Memory device with reduced leakage current 有权
标题翻译：具有降低漏电流的存储器件
公开(公告)号：US20060203536A1
公开(公告)日：2006-09-14
申请号：US11322178
申请日：2005-12-29
申请人： Devesh Dwivedi , Ashish Kumar
发明人： Devesh Dwivedi , Ashish Kumar
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C5/147
摘要： A technique for reducing the bitline leakage current while maintaining a level of performance characteristics of low threshold voltage transistors in deep submicron CMOS technology incorporates a reference voltage generator circuit in combination with bias transistor MBIAS. The output of a static logic gate is connected to the input terminal of the pull-down devices. The reduction in leakage current through pull-down devices whenever a read operation is not performed contributes to a significant reduction in overall leakage current in the circuit.
摘要翻译：在深亚微米CMOS技术中保持低阈值电压晶体管的性能特性水平的同时降低位线漏电流的技术包括与偏置晶体管MBIAS组合的参考电压发生器电路。静态逻辑门的输出端连接到下拉装置的输入端。每当读取操作不执行时，通过下拉器件的漏电流的减少有助于电路中的总漏电流的显着降低。

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