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11. 发明授权

US06960908B2 Method for electrical testing of semiconductor package that detects socket defects in real time 有权
标题翻译：实时检测插座缺陷的半导体封装的电气测试方法
公开(公告)号：US06960908B2
公开(公告)日：2005-11-01
申请号：US10824220
申请日：2004-04-13
申请人： Ae-yong Chung , Sung-Ok Kim , Jeong-ho Bang , Kyeong-seon Shin , Dae-gab Chi
发明人： Ae-yong Chung , Sung-Ok Kim , Jeong-ho Bang , Kyeong-seon Shin , Dae-gab Chi
IPC分类号： G01R31/26 , G01R31/02 , G01R31/28
CPC分类号： G11C29/56016 , G01R31/2893 , G01R31/2894 , G11C2029/5602
摘要： An electrical testing method for a semiconductor package for detecting defects of sockets mounted on a device under test (DUT) board is provided. A tester performs electrical test, accumulates electrical test results, and compares the accumulated results to reference values. The result of the comparison decides whether a plurality of sockets mounted on the DUT board can be used or not. The decision results are transmitted to a handler so that the socket having the defects is not used on the DUT board.
摘要翻译：提供了一种用于检测安装在被测设备（DUT）板上的插座的缺陷的半导体封装的电气测试方法。测试仪进行电气测试，累积电气测试结果，并将累积结果与参考值进行比较。比较结果决定了是否可以使用安装在DUT板上的多个插槽。决定结果被传送到处理器，以便在DUT板上不使用具有缺陷的插座。

12. 发明授权

US06922050B2 Method for testing a remnant batch of semiconductor devices 有权
标题翻译：用于测试残留批次的半导体器件的方法
公开(公告)号：US06922050B2
公开(公告)日：2005-07-26
申请号：US10835143
申请日：2004-04-28
申请人： Ae-yong Chung , Sung-ok Kim , Jeong-ho Bang , Kyeong-seon Shin , Dae-gab Chi
发明人： Ae-yong Chung , Sung-ok Kim , Jeong-ho Bang , Kyeong-seon Shin , Dae-gab Chi
IPC分类号： G01R31/26 , G01R31/01 , H01L21/66 , G01R31/02
CPC分类号： G01R31/01
摘要： A method for testing semiconductor devices includes loading a customer tray with semiconductor devices to be tested. Groups of devices are transferred from the customer tray to buffer trays for testing. The number of devices in the customer tray is checked after each transfer. If the customer tray is empty, the number of semiconductor devices in the buffer trays is counted and compared with the number of semiconductor devices that can be tested simultaneously, typically either 64 or 128. If the number of semiconductor devices in the buffer trays is greater than the tester capacity, the semiconductor devices in at least one buffer tray are tested. If the number of semiconductor devices in the buffer trays is smaller than the tester capacity, semiconductor devices that were determined to be low quality in a prior test are loaded into a buffer tray, thus testing both untested and low quality devices together.
摘要翻译：一种用于测试半导体器件的方法包括：将客户托盘加载到待测试的半导体器件上。设备组从客户托盘传输到缓冲盘进行测试。客户托盘中的设备数量在每次传输后都会被检查。如果客户托盘为空，则对缓冲托盘中的半导体器件的数量进行计数，并与可同时测试的半导体器件的数量进行比较，通常为64或128.如果缓冲托盘中的半导体器件的数量较大比测试器的容量，测试至少一个缓冲盘中的半导体器件。如果缓冲盘中的半导体器件的数量小于测试器容量，则在先前测试中被确定为低质量的半导体器件被加载到缓冲托盘中，从而同时测试未测试的和低质量的器件。

13. 发明申请

US20080197874A1 TEST APPARATUS HAVING MULTIPLE TEST SITES AT ONE HANDLER AND ITS TEST METHOD 有权
标题翻译：具有多个测试站点的测试设备及其测试方法
公开(公告)号：US20080197874A1
公开(公告)日：2008-08-21
申请号：US12109299
申请日：2008-04-24
申请人： Ae-Yong CHUNG , Sung-Ok KIM , Kyeong-Seon SHIN , Jeong-Ho BANG
发明人： Ae-Yong CHUNG , Sung-Ok KIM , Kyeong-Seon SHIN , Jeong-Ho BANG
IPC分类号： G01R31/26
CPC分类号： G01R31/2893 , G01R31/01 , G01R31/2851
摘要： A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.
摘要翻译：测试装置包括连接到测试器的一个处理器和分成两个或更多个站点或两个或更多个测试板的一个测试板。由于只有测试板（或测试板）上的站点需要复制，而不是处理器的加载通道或分拣机，所以测试设备可以方便地紧凑。此外，在一个站点或一个测试板上测试半导体器件时，可以根据测试结果对另一个站点中的另一个站点或另一个测试板上的半导体器件进行分类。这使得能够减少或消除测试器空闲时间以优化测试设备的效率。

14. 发明授权

US07408339B2 Test system of semiconductor device having a handler remote control and method of operating the same 有权
标题翻译：具有处理器遥控器的半导体器件的测试系统及其操作方法
公开(公告)号：US07408339B2
公开(公告)日：2008-08-05
申请号：US11749053
申请日：2007-05-15
申请人： Ae-Yong Chung , Eun-Seok Lee , Jeong-Ho Bang , Kyeong-Seon Shin , Dae-Gab Chi , Sung-Ok Kim
发明人： Ae-Yong Chung , Eun-Seok Lee , Jeong-Ho Bang , Kyeong-Seon Shin , Dae-Gab Chi , Sung-Ok Kim
IPC分类号： G01R31/28
CPC分类号： G01R31/2893 , G01R31/2894 , G01R31/31718 , G01R31/31919
摘要： A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.
摘要翻译：提供了一种用于处理器遥控器的半导体器件的测试系统。该系统包括：用于测试半导体器件的测试仪; 通过GPIB（通用指令总线）通信电缆连接到测试仪的处理器; 连接到测试器的测试仪服务器向测试者下载测试程序，处理程序遥控程序和处理程序状态检查程序; 以及通过测试者和处理者之间的GPIB通信电缆发送和接收的通信数据，其中通信数据具有用于半导体器件的电气测试的基本通信数据，用于处理器远程控制的通信数据和用于处理器状态的通信数据检查。

15. 发明授权

US07378864B2 Test apparatus having multiple test sites at one handler and its test method 有权
标题翻译：在一个处理机上具有多个测试点的测试设备及其测试方法
公开(公告)号：US07378864B2
公开(公告)日：2008-05-27
申请号：US11092067
申请日：2005-03-28
申请人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
发明人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/2893 , G01R31/01 , G01R31/2851
摘要： A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.
摘要翻译：测试装置包括连接到测试器的一个处理器和分成两个或更多个站点或两个或更多个测试板的一个测试板。由于只有测试板（或测试板）上的站点需要复制，而不是处理器的加载通道或分拣机，所以测试设备可以方便地紧凑。此外，在一个站点或一个测试板上测试半导体器件时，可以根据测试结果对另一个站点中的另一个站点或另一个测试板上的半导体器件进行分类。这使得能够减少或消除测试器空闲时间以优化测试设备的效率。

16. 发明授权

US07230417B2 Test system of semiconductor device having a handler remote control and method of operating the same 有权
标题翻译：具有处理器遥控器的半导体器件的测试系统及其操作方法
公开(公告)号：US07230417B2
公开(公告)日：2007-06-12
申请号：US11252448
申请日：2005-10-17
申请人： Ae-Yong Chung , Eun-Seok Lee , Jeong-Ho Bang , Kyeong-Seon Shin , Dae-Gab Chi , Sung-Ok Kim
发明人： Ae-Yong Chung , Eun-Seok Lee , Jeong-Ho Bang , Kyeong-Seon Shin , Dae-Gab Chi , Sung-Ok Kim
IPC分类号： G01R31/28
CPC分类号： G01R31/31926 , G01R31/31907
摘要： A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.
摘要翻译：提供了一种用于处理器遥控器的半导体器件的测试系统。该系统包括：用于测试半导体器件的测试仪; 通过GPIB（通用指令总线）通信电缆连接到测试仪的处理器; 连接到测试器的测试仪服务器向测试者下载测试程序，处理程序遥控程序和处理程序状态检查程序; 以及通过GPIB通信电缆在测试者和处理者之间发送和接收的通信数据，其中通信数据具有用于半导体器件的电气测试的基本通信数据，用于处理器远程控制的通信数据和用于处理器状态的通信数据检查。

17. 发明申请

US20050168236A1 Test apparatus having multiple test sites at one handler and its test method 有权
标题翻译：在一个处理机上具有多个测试点的测试装置及其测试方法
公开(公告)号：US20050168236A1
公开(公告)日：2005-08-04
申请号：US11092067
申请日：2005-03-28
申请人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
发明人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
IPC分类号： G01R31/26 , G01R31/01 , G01R31/28
CPC分类号： G01R31/2893 , G01R31/01 , G01R31/2851
摘要： A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.
摘要翻译：测试装置包括连接到测试器的一个处理器和分成两个或更多个站点或两个或更多个测试板的一个测试板。由于只有测试板（或测试板）上的站点需要复制，而不是处理器的加载通道或分拣机，所以测试设备可以方便地紧凑。此外，在一个站点或一个测试板上测试半导体器件时，可以根据测试结果对另一个站点中的另一个站点或另一个测试板上的半导体器件进行分类。这使得能够减少或消除测试器空闲时间以优化测试设备的效率。

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