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11. 发明申请

US20140115547A1 Method of Generating Parameterized Units 审中-公开
标题翻译：生成参数化单位的方法
公开(公告)号：US20140115547A1
公开(公告)日：2014-04-24
申请号：US13897399
申请日：2013-05-18
申请人： Semitronix Corporation
发明人： YONGJUN ZHENG
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F2217/06
摘要： The present invention relates to a method of method of generating parameterized integrated circuit units in a plurality of platforms. The said method comprising: (1) designing parameterized units in a graphic user interface and defining their constrain relations; (2) transforming the parameterized units to scripts. The invention providing a method of designing parameterized units in a graphical user interface without editing parameterized unit scripts, reducing the complexity of the design process and the design cycle; in addition, it is very easy for users to design and maintenance; at the same time, increasing the portability.
摘要翻译：本发明涉及在多个平台中生成参数化集成电路单元的方法的方法。所述方法包括：（1）在图形用户界面中设计参数化单元并定义其约束关系; （2）将参数化单位转换为脚本。本发明提供了一种在图形用户界面中设计参数化单元而不编辑参数化单元脚本的方法，降低了设计过程和设计周期的复杂性; 另外，用户非常容易设计和维护; 同时增加便携性。

12. 发明授权

US11274971B2 Temperature sensor 有权
公开(公告)号：US11274971B2
公开(公告)日：2022-03-15
申请号：US16726917
申请日：2019-12-25
申请人： Semitronix Corporation
发明人： Zhong Tang , Zheng Shi , Weiwei Pan , Zhenyan Huang
IPC分类号： G01K7/01 , G01K15/00 , H03K19/20 , H03K19/08 , H03K19/173
摘要： A temperature sensor includes a NAND gate and a plurality of delay units. The NAND gate includes a first and a second input terminals, and an output terminal. The first input terminal is configured to receive an external starting control signal. The plurality of delay units are connected in series. An input end of the first delay unit is connected to the output terminal of the NAND gate. An output end of the last delay unit is connected to the second input terminal of the NAND gate, thereby forming a ring oscillator structure. The temperature sensor can realize conversion of temperature-leakage-frequency based on the ring oscillator structure in a temperature range of −40˜125° C., thereby simplifying design complexity and achieves high accuracy.

13. 发明申请

US20200209069A1 TEMPERATURE SENSOR 审中-公开
公开(公告)号：US20200209069A1
公开(公告)日：2020-07-02
申请号：US16726908
申请日：2019-12-25
申请人： Semitronix Corporation
发明人： Zhong TANG , Yun FANG , Xiaopeng YU , Zheng SHI
IPC分类号： G01K7/00 , H03K19/20 , H03K5/133 , H03K3/037 , H03K3/03
摘要： A reconfigurable all-digital temperature sensor includes a NAND gate and several delay units, the NAND gate comprises two input terminals and an output terminal, one input terminal is used for external starting control signal; a plurality delay units are connected in series, the input end of the first delay unit is connected to the output terminal of the NAND gate, and the output end of the last delay unit is connected to another input terminal of the NAND gate, thereby forming a ring oscillator structure; each delay unit includes a leakage-based inverter and a Schmitt trigger, and the output end of the leakage-based inverter is connected to the input end of the Schmitt trigger. The reconfigurable all-digital temperature sensor can realize the conversion of temperature-leakage-frequency based on the ring oscillator structure in the temperature range of −40˜125° C., thereby reducing the design complexity and achieving high accuracy.

14. 发明授权

US09817058B2 Addressable test circuit and test method for key parameters of transistors 有权
公开(公告)号：US09817058B2
公开(公告)日：2017-11-14
申请号：US15351421
申请日：2016-11-14
申请人： Semitronix Corporation
发明人： Weiwei Pan , Yongjun Zheng
IPC分类号： G01R31/26 , H01L21/66 , G11C29/50
CPC分类号： G01R31/2621 , G01R31/2601 , G01R31/2607 , G11C29/50008 , G11C2029/5002 , G11C2029/5006 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An addressable test circuit is configured to test parameters of a plurality of transistors. The addressable test circuit includes combination logic circuits including a plurality of gate circuits and are configured to select a device under test, a plurality of PADs, a plurality of address bus and data bus; wherein six or more of the data buses are test signal lines. A test method can employ the above address test circuit for testing parameters of a plurality of transistors, where the subthreshold leakage current Ioff and saturation current Idsat are measured in different signal lines respectively to ensure the accurate measurement of the two parameters in one circuit.

15. 发明授权

US09646900B2 Programmable addressable test chip 有权
公开(公告)号：US09646900B2
公开(公告)日：2017-05-09
申请号：US14604705
申请日：2015-01-24
申请人： Semitronix Corporation
发明人： Xu Ouyang , Yongjun Zheng , Zheng Shi , Peiyong Zhang
IPC分类号： H01L21/66 , G01R31/28
CPC分类号： H01L22/32 , G01R31/2884 , H01L22/14 , H01L22/34
摘要： A programmable test chip includes a target chip to be tested and addressing circuits fabricated on the same wafer. The addressing circuits can be placed in the scribe lines or a pre-allocated area of the wafer. When testing the target chip, a circuit connecting the target chip and the addressing circuits can be fabricated on demand. In some cases the target chip is not connected to the addressing circuits, and a DUT array exists in a scribe line having a connecting circuit prefabricated between the addressing circuits with the DUT array for testing the DUT array in the scribe line. When the need for testing the target chip arises, the prefabricated connecting circuit can be cut, and the connecting circuit connecting the target chip and the addressing circuits can be fabricated. Based on results from such test chips, the manufacturing process can be better studied.

16. 发明授权

US09146270B2 Method for testing a plurality of transistors in a target chip 有权
标题翻译：用于测试目标芯片中的多个晶体管的方法
公开(公告)号：US09146270B2
公开(公告)日：2015-09-29
申请号：US14178029
申请日：2014-02-11
申请人： Semitronix Corporation
发明人： Kangpeng Shao , Yongjun Zheng , Xu Ouyang
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/2607 , G01R31/2818
摘要： The present invention relates to the chip testing field. A method for testing a plurality of transistors in a target chip is provided, characterized by automatically selecting a plurality of pre-defined transistors on the target chip and adding a connection layer to the key layers of each transistor such that the transistor to be tested is connected with and measured by an outside tester. Through automatic generation of the test structures and automatic wiring, the present invention greatly shortens the design cycle of test chips for target transistor testing, and greatly reduces the error probability in the process of designing test chips for target transistor testing, and improves the testing relevancy.
摘要翻译：本发明涉及芯片测试领域。提供了一种用于测试目标芯片中的多个晶体管的方法，其特征在于，在目标芯片上自动选择多个预定义晶体管，并将连接层添加到每个晶体管的键层，使得被测试的晶体管为与外部测试仪连接并测量。通过自动生成测试结构和自动布线，本发明大大缩短了目标晶体管测试测试芯片的设计周期，大大降低了目标晶体管测试芯片设计过程中的误差概率，提高了测试相关性。

17. 发明授权

US11668748B2 Addressable test chip 有权
公开(公告)号：US11668748B2
公开(公告)日：2023-06-06
申请号：US17648935
申请日：2022-01-25
申请人： SEMITRONIX CORPORATION
发明人： Fan Lan , Weiwei Pan , Shenzhi Yang , Yongjun Zheng
IPC分类号： G01R31/317 , G01R31/28
CPC分类号： G01R31/31722 , G01R31/2882 , G01R31/2886
摘要： A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

18. 发明授权

US11156505B2 Temperature sensor 有权
公开(公告)号：US11156505B2
公开(公告)日：2021-10-26
申请号：US16726908
申请日：2019-12-25
申请人： Semitronix Corporation
发明人： Zhong Tang , Yun Fang , Xiaopeng Yu , Zheng Shi
IPC分类号： G01K11/22 , G01K7/00 , H03K19/20 , H03K3/037 , H03K3/03 , H03K5/133 , H03K5/00
摘要： A reconfigurable all-digital temperature sensor includes a NAND gate and several delay units, the NAND gate comprises two input terminals and an output terminal, one input terminal is used for external starting control signal; a plurality delay units are connected in series, the input end of the first delay unit is connected to the output terminal of the NAND gate, and the output end of the last delay unit is connected to another input terminal of the NAND gate, thereby forming a ring oscillator structure; each delay unit includes a leakage-based inverter and a Schmitt trigger, and the output end of the leakage-based inverter is connected to the input end of the Schmitt trigger. The reconfigurable all-digital temperature sensor can realize the conversion of temperature-leakage-frequency based on the ring oscillator structure in the temperature range of −40˜125° C., thereby reducing the design complexity and achieving high accuracy.

19. 发明授权

US10725101B2 Addressable test chip with multiple-stage transmission gates 有权
公开(公告)号：US10725101B2
公开(公告)日：2020-07-28
申请号：US16377422
申请日：2019-04-08
申请人： Semitronix Corporation
发明人： Fan Lan
IPC分类号： G01R31/317 , G01R31/28
摘要： A test apparatus for testing electrical parameters of a target chip, the apparatus including: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

20. 发明申请

US20190235022A1 ADDRESSABLE TEST CHIP WITH SENSING CIRCUIT 审中-公开
公开(公告)号：US20190235022A1
公开(公告)日：2019-08-01
申请号：US16377471
申请日：2019-04-08
申请人： Semitronix Corporation
发明人： Fan LAN
IPC分类号： G01R31/317 , G01R31/28
CPC分类号： G01R31/31722 , G01R31/2882 , G01R31/2886
摘要： An address register includes a plurality of edge-triggered flip-flop registers having an input D, an input R, an input CK, and an output Q; a counter logic; a shifter logic; a multiplexer; input ports including a reset signal RST, a clock signal CLK, a shift enable signal SE, a shift data input signal SI; an output port including address signals ADDR. D is coupled to a data output of the multiplexer; R is coupled to a reset (RST) pad; CK is coupled to a clock (CLK) pad; Q is coupled to an address (ADDR) pad; an input of the counter logic is coupled to ADDR; an input of the shifter logic is coupled to ADDR and the shift data input signal SI; an input of the multiplexer is coupled to SE, an output of the counter logic, and an output of the shifter logic.

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