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11. 发明授权

US07732879B2 Semiconductor device and method for manufacturing semiconductor device 失效
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US07732879B2
公开(公告)日：2010-06-08
申请号：US12367888
申请日：2009-02-09
申请人： Gwang Su Kim
发明人： Gwang Su Kim
IPC分类号： H01L29/78
CPC分类号： H01L21/823437 , C23C16/345 , C23C16/507 , H01L21/02304 , H01L21/28035 , H01L21/31625 , H01L21/3185 , H01L21/823418 , H01L29/78
摘要： Provided are a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes: a gate electrode formed of polysilicon on a substrate with a gate insulating layer interposed between the gate electrode and the substrate; a source region and a drain region formed on the substrate on either side of the gate electrode; a PMD (poly-metal dielectric) liner nitride layer having a non-stoichiometric structure formed on the gate electrode, the source region, and the drain region; and an interlayer insulating layer formed on the PMD liner nitride layer.
摘要翻译：提供半导体器件和制造半导体器件的方法。半导体器件包括：在基板上由多晶硅形成的栅电极，栅极绝缘层插入在栅电极和衬底之间; 源极区域和漏极区域，形成在栅电极的任一侧的基板上; 在栅电极，源极区和漏极区上形成具有非化学计量结构的PMD（多金属电介质）衬垫氮化物层; 以及形成在PMD衬垫氮化物层上的层间绝缘层。

12. 发明授权

US07723220B2 Method of forming compressive channel layer of PMOS device using gate spacer and PMOS device having a compressed channel layer 有权
标题翻译：使用具有压缩沟道层的栅极间隔物和PMOS器件形成PMOS器件的压电沟道层的方法
公开(公告)号：US07723220B2
公开(公告)日：2010-05-25
申请号：US11637359
申请日：2006-12-11
申请人： Jin Ha Park
发明人： Jin Ha Park
IPC分类号： H01L21/425
CPC分类号： H01L29/4983 , H01L21/31155 , H01L29/6656 , H01L29/7843
摘要： A method of forming a compressive channel layer in a PMOS device and a PMOS device having a compressive channel layer are provided. The method includes (a) forming a buffer oxide layer on a silicon semiconductor substrate having a gate oxide layer and a gate electrode thereon, (b) forming a silicon nitride layer on the buffer oxide layer, (c) implanting impurities into the silicon nitride layer, and (d) etching or patterning the silicon nitride layer and the buffer oxide layer into which impurities are implanted to form gate spacers on sidewalls of the gate electrode.
摘要翻译：提供了在PMOS器件中形成压缩沟道层的方法和具有压缩沟道层的PMOS器件。该方法包括：（a）在其上具有栅极氧化层和栅电极的硅半导体衬底上形成缓冲氧化物层，（b）在缓冲氧化物层上形成氮化硅层，（c）将杂质注入氮化硅层，以及（d）蚀刻或图案化氮化硅层和其中注入杂质的缓冲氧化物层，以在栅电极的侧壁上形成栅极间隔物。

13. 发明授权

US07723190B2 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07723190B2
公开(公告)日：2010-05-25
申请号：US11647691
申请日：2006-12-28
申请人： Gyu Gwang Sim , Jong Min Kim
发明人： Gyu Gwang Sim , Jong Min Kim
IPC分类号： H01L21/8234
CPC分类号： H01L29/66666 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/42368 , H01L29/7828
摘要： Disclosed are a semiconductor device having a vertical trench gate structure to improve the integration degree and a method of manufacturing the same. The semiconductor device includes an epitaxial layer having a second conductive type on a first conductive type substrate having an active region and an isolation region, a trench in the isolation region, a first conductive type first region in the epitaxial layer at opposite side portions of the trench, an isolation layer at a predetermined depth in the trench, a gate insulation layer along upper side portions of the trench, a gate electrode in an upper portion of the trench, a body region in the active region, a source electrode on the body region, a source region in an upper portion of the body region at opposite side portions of the gate electrode, and a drain electrode at a rear surface of the substrate.
摘要翻译：公开了一种具有提高集成度的垂直沟槽栅极结构的半导体器件及其制造方法。半导体器件包括在第一导电类型衬底上具有第二导电类型的外延层，该第一导电类型衬底具有有源区和隔离区，隔离区中的沟槽，在外延层中的第二导电类型的第一区，沟槽，沟槽中预定深度处的隔离层，沿着沟槽的上侧部分的栅极绝缘层，沟槽上部的栅极电极，有源区域中的主体区域，主体上的源极电极区域，位于栅电极的相对侧部的体区的上部的源极区域和位于衬底的背面的漏电极。

14. 发明授权

US07709372B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07709372B2
公开(公告)日：2010-05-04
申请号：US11641037
申请日：2006-12-19
申请人： Keun Soo Park
发明人： Keun Soo Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/76877 , H01L21/76849 , H01L21/76855 , H01L21/76889
摘要： A method of manufacturing a metal wiring in a semiconductor device includes: forming a via hole by selectively etching an interlayer insulating layer formed on a first metal layer; sequentially forming a first barrier metal layer and a second metal layer on the interlayer insulating layer; etching the first barrier metal layer and the second metal layer in the via hole to a predetermined depth together with selectively etching a surface of the second metal layer; forming a silicon layer on the first barrier metal and the second metal to a predetermined height; forming a second barrier metal layer on the interlayer insulating layer; forming a third metal layer on the second barrier metal layer; and forming a second barrier metal pattern and a third metal layer pattern by patterning the second barrier metal layer and the third metal layer.
摘要翻译：在半导体器件中制造金属布线的方法包括：通过选择性地蚀刻形成在第一金属层上的层间绝缘层来形成通孔; 在层间绝缘层上依次形成第一阻挡金属层和第二金属层; 在选择性蚀刻第二金属层的表面的同时，将通孔中的第一阻挡金属层和第二金属层蚀刻到预定深度; 在所述第一阻挡金属和所述第二金属上形成硅层至预定高度; 在所述层间绝缘层上形成第二阻挡金属层; 在所述第二阻挡金属层上形成第三金属层; 以及通过图案化所述第二阻挡金属层和所述第三金属层来形成第二阻挡金属图案和第三金属层图案。

15. 发明授权

US07709321B2 Flash memory device and fabricating method thereof 失效
标题翻译：闪存装置及其制造方法
公开(公告)号：US07709321B2
公开(公告)日：2010-05-04
申请号：US11024700
申请日：2004-12-30
申请人： Jin Hyo Jung
发明人： Jin Hyo Jung
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273 , Y10S438/954
摘要： A flash memory and a flash memory fabrication method for increasing the coupling ratio by HSG including forming a STI region on a silicon substrate to define an active region, forming a tunneling oxide layer on the active region, and depositing an amorphous silicon layer on the silicon substrate. The method also includes patterning the amorphous silicon layer along a bit line direction, forming an embossed silicon layer including HSGs on the patterned amorphous silicon layer, and sequentially depositing an ONO layer and a polysilicon layer for a control gate on the resulting structure. The method further includes forming a photoresist pattern on the polysilicon layer, and forming a control gate by etching the polysilicon layer using the photoresist pattern as a mask, and simultaneously forming a floating gate along the bit line.
摘要翻译：一种用于通过HSG增加耦合比的闪速存储器和闪速存储器制造方法，包括在硅衬底上形成STI区以限定有源区，在有源区上形成隧穿氧化物层，以及在硅上沉积非晶硅层基质。该方法还包括沿位线方向图案化非晶硅层，在图案化非晶硅层上形成包括HSG的压花硅层，并在所得结构上依次沉积ONO层和用于控制栅极的多晶硅层。所述方法还包括在所述多晶硅层上形成光致抗蚀剂图案，以及通过使用所述光致抗蚀剂图案作为掩模蚀刻所述多晶硅层，并且沿着所述位线同时形成浮栅来形成控制栅极。

16. 发明授权

US07705378B2 CMOS image sensor and fabricating method thereof 有权
标题翻译： CMOS图像传感器及其制造方法
公开(公告)号：US07705378B2
公开(公告)日：2010-04-27
申请号：US11319590
申请日：2005-12-29
申请人： Chang Eun Lee
发明人： Chang Eun Lee
IPC分类号： H01L31/062 , H01L21/00
CPC分类号： H01L27/14627 , H01L27/1463 , H01L27/14685
摘要： A CMOS image sensor and fabricating method thereof can enhance the quality of the image sensor by preventing unnecessary diffused reflection of light by providing an opaque filter layer next to a microlens. The CMOS image sensor includes a photodiode, an insulating interlayer, a metal line, a device protecting layer, a microlens on the device protecting layer and overlapped with the photodiode, and an opaque layer pattern on the device protecting layer next to the microlens.
摘要翻译： CMOS图像传感器及其制造方法可以通过在微透镜旁边提供不透明的滤光层来防止光的不必要的漫反射来提高图像传感器的质量。 CMOS图像传感器包括光电二极管，绝缘中间层，金属线，器件保护层，器件保护层上的微透镜并与光电二极管重叠，以及在微透镜旁边的器件保护层上的不透明层图案。

17. 发明授权

US07683401B2 Semiconductor device and method of fabricating thereof capable of reducing a shallow trench isolation stress influence by utilizing layout pattern designs 有权
标题翻译：半导体器件及其制造方法能够通过利用布局图案设计来减小浅沟槽隔离应力的影响
公开(公告)号：US07683401B2
公开(公告)日：2010-03-23
申请号：US11519361
申请日：2006-09-12
申请人： Myung Jin Jung
发明人： Myung Jin Jung
IPC分类号： H01L27/088
CPC分类号： H01L29/0692 , H01L27/0207
摘要： Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of contact metals, and a gate electrode. The semiconductor substrate has an active region and a dummy active region, and a plurality of contact metals are formed in the active region. A gate electrode is located between the contact metals in the active region. A first distance between the active region and the dummy active region, and a second distance between an edge of the contact metal and an edge of the active region are set such that a channel characteristic of the active region is improved.
摘要翻译：提供一种半导体器件。半导体器件包括半导体衬底，多个接触金属和栅电极。半导体衬底具有有源区和伪有源区，并且在有源区中形成多个接触金属。栅电极位于有源区域中的接触金属之间。激活区域和虚拟有源区域之间的第一距离以及接触金属的边缘与有源区域的边缘之间的第二距离被设定为使得有源区域的沟道特性得到改善。

18. 发明授权

US07678643B2 Method for manufacturing a CMOS image sensor 有权
标题翻译： CMOS图像传感器的制造方法
公开(公告)号：US07678643B2
公开(公告)日：2010-03-16
申请号：US11528178
申请日：2006-09-26
申请人： In Gyun Jeon
发明人： In Gyun Jeon
IPC分类号： H01L21/8238 , H01L31/062
CPC分类号： H01L27/14643 , H01L27/14601 , H01L27/14689
摘要： Provided is a CMOS image sensor and method of manufacturing same. The CMOS image sensor includes a photodiode, a transfer transistor, a reset transistor, a drive transistor, and a select transistor. A device isolation layer is formed on a first conductive type substrate. Gate electrodes of the transfer transistor, the reset transistor, the drive transistor, and the select transistor are formed on an active region of the substrate with gate insulating layers interposed therebetween. A first diffusion region is formed of a second conductive type in a first region of the active region, where the first region does not include a floating diffusion region between the transfer transistor and the reset transistor and the photodiode region. A second diffusion region is formed of the second conductive type in the floating diffusion region at a concentration lower than that of the second conductive type first diffusion region.
摘要翻译：提供了一种CMOS图像传感器及其制造方法。 CMOS图像传感器包括光电二极管，传输晶体管，复位晶体管，驱动晶体管和选择晶体管。器件隔离层形成在第一导电类型的衬底上。传输晶体管的栅电极，复位晶体管，驱动晶体管和选择晶体管形成在衬底的有源区上，栅极绝缘层位于它们之间。第一扩散区域由有源区域的第一区域中的第二导电类型形成，其中第一区域不包括传输晶体管和复位晶体管与光电二极管区域之间的浮动扩散区域。第二扩散区域以比第二导电型第一扩散区域低的浓度在浮动扩散区域中由第二导电类型形成。

19. 发明授权

US07678602B2 CMOS image sensor and method for manufacturing the same 失效
标题翻译： CMOS图像传感器及其制造方法
公开(公告)号：US07678602B2
公开(公告)日：2010-03-16
申请号：US11615086
申请日：2006-12-22
申请人： Chang Eun Lee
发明人： Chang Eun Lee
IPC分类号： H01L27/146
CPC分类号： H01L27/14632 , H01L27/14621 , H01L27/14643
摘要： A CMOS image sensor and a method for manufacturing the same are provided. The method includes: preparing a semiconductor substrate in which a device isolation region and an active region are defined; forming a gate pattern including a gate oxide layer and a gate electrode on the semiconductor substrate; implanting n-type impurity ions in a predetermined part of the active region of the semiconductor substrate to form a photodiode region; forming a spacer at a sidewall of the gate pattern; forming a p-type impurity region at a surface of the photodiode region; forming an epitaxial layer on the semiconductor substrate and the gate pattern except for on the device isolation region and the spacers by performing a selective epitaxial growth; and implanting n+ type ions in a transistor region of the semiconductor substrate below the epitaxial layer to form a source/drain region.
摘要翻译：提供CMOS图像传感器及其制造方法。该方法包括：制备其中限定了器件隔离区和有源区的半导体衬底; 在所述半导体衬底上形成包括栅极氧化物层和栅电极的栅极图案; 在所述半导体衬底的有源区的预定部分中注入n型杂质离子以形成光电二极管区; 在所述栅极图案的侧壁处形成间隔物; 在所述光电二极管区域的表面形成p型杂质区域; 通过进行选择性外延生长，在半导体衬底上形成除了器件隔离区域和间隔物之外的栅极图案的外延层; 以及在所述半导体衬底的所述外延层下面的晶体管区域内注入n +型离子以形成源/漏区。

20. 发明授权

US07655526B2 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07655526B2
公开(公告)日：2010-02-02
申请号：US11638110
申请日：2006-12-12
申请人： Choul Joo Ko
发明人： Choul Joo Ko
IPC分类号： H01L21/331
CPC分类号： H01L21/31111 , H01L21/28247 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： Disclosed is a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the steps of forming a gate electrode on a semiconductor substrate, forming a drift area in the semiconductor substrate by implanting a dopant using the gate electrode as a mask, forming a sidewall spacer at sides of the gate electrode, and forming a source/drain area in the semiconductor substrate by implanting a dopant using the gate electrode and the sidewall spacer as a mask.
摘要翻译：公开了半导体器件的制造方法。半导体器件的制造方法包括以下步骤：在半导体衬底上形成栅电极，通过使用栅电极作为掩模注入掺杂剂，在半导体衬底中形成漂移区，在栅电极的侧面形成侧墙并且通过使用栅电极和侧壁间隔物作为掩模注入掺杂剂来在半导体衬底中形成源极/漏极区域。

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