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181. 发明申请

US20120168881A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120168881A1
公开(公告)日：2012-07-05
申请号：US13142591
申请日：2011-01-27
申请人： Haizhou Yin , Huicai Zhong , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huicai Zhong , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/7846 , H01L21/76224 , H01L29/045 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.
摘要翻译：本发明提供一种半导体器件及其制造方法。制造半导体器件的方法包括：提供其上形成有栅极叠层结构并具有{100}晶体指数的硅衬底; 形成层叠所述硅衬底的顶表面的层间电介质层; 在所述层间介质层和/或所述栅堆叠结构中形成第一沟槽，所述第一沟槽具有沿着晶体方向并且垂直于所述栅堆叠结构的延伸方向; 以及用第一介电层填充所述第一沟槽，其中所述第一介电层是拉伸应力介电层。本发明通过使用简单的工艺在沟道区域的横向上引入拉伸应力，这提高了半导体器件的响应速度和性能。

182. 发明申请

US20120112252A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120112252A1
公开(公告)日：2012-05-10
申请号：US13380380
申请日：2011-02-27
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L23/485 , H01L21/76804 , H01L21/823475 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor structure, which lies in covering a first dielectric layer with a second dielectric layer, forming a first contact hole with a small inner diameter within the second dielectric layer first, then etching the first dielectric layer to form a second contact hole with a much great inner diameter, and finally filling a conductive material into the first contact hole and the second contact hole to form contact plugs. Accordingly, the present invention further provides a semiconductor structure favorable for reducing contact resistance.
摘要翻译：本发明提供了一种制造半导体结构的方法，该半导体结构覆盖第一介电层与第二介电层，首先在第二电介质层内形成具有小内径的第一接触孔，然后蚀刻第一介电层至形成具有非常大的内径的第二接触孔，最后将导电材料填充到第一接触孔和第二接触孔中以形成接触塞。因此，本发明还提供有利于降低接触电阻的半导体结构。

183. 发明申请

US20120061735A1 SEMICONDUCTOR DEVICE WITH STRESS TRENCH ISOLATION AND METHOD FOR FORMING THE SAME 有权
标题翻译：具有应力裂解隔离的半导体器件及其形成方法
公开(公告)号：US20120061735A1
公开(公告)日：2012-03-15
申请号：US13257725
申请日：2011-01-27
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823412 , H01L21/823807 , H01L21/823878
摘要： A semiconductor device with stress trench isolation and a method for forming the same are provided. The method includes: providing a silicon substrate; forming first trenches and second trenches on the silicon substrate, wherein an extension direction of the first trenches is perpendicular to that of the second trenches; forming a first dielectric layer in the first trenches and forming a second dielectric layer in the second trenches; and forming a gate stack on a portion of the silicon substrate surrounded by the first trenches and the second trenches, wherein a channel length direction under the gate stack is parallel to the extension direction of the first trenches, indices of crystal plane of the silicon substrate are {100}, and the extension direction of the first trenches is along the crystal orientation . The embodiments of the present invention can improve response speed and performance of the devices.
摘要翻译：提供了一种具有应力沟槽隔离的半导体器件及其形成方法。该方法包括：提供硅衬底; 在所述硅衬底上形成第一沟槽和第二沟槽，其中所述第一沟槽的延伸方向垂直于所述第二沟槽的延伸方向; 在所述第一沟槽中形成第一电介质层，并在所述第二沟槽中形成第二电介质层; 以及在由所述第一沟槽和所述第二沟槽围绕的所述硅衬底的一部分上形成栅极堆叠，其中所述栅叠层下方的沟道长度方向平行于所述第一沟槽的延伸方向，所述硅衬底的晶面的折射率是{100}，并且第一沟槽的延伸方向是沿着晶体取向<110>。本发明的实施例可以提高设备的响应速度和性能。

184. 发明申请

US20120049249A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120049249A1
公开(公告)日：2012-03-01
申请号：US13062733
申请日：2010-09-20
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Huicai Zhong
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Huicai Zhong
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7834 , H01L21/76224 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： A semiconductor structure and a method for fabricating the same. A semiconductor structure includes a semiconductor substrate; a channel region formed in the semiconductor substrate; a gate including a dielectric layer and a conductive layer and formed above the channel region; source and drain regions formed at opposing sides of the gate; first shallow trench isolations embedded into the semiconductor substrate and having a length direction parallel to the length direction of the gate; and second shallow trench isolations, each of which abuts the outer sidewall of the source or the drain region and abuts the first shallow trench isolations, in which the source and drain regions include first seed crystal layers abutting the second shallow trench isolations, and the top surfaces of the second shallow trench isolations are higher than or as high as the top surfaces of the source and drain regions.
摘要翻译：半导体结构及其制造方法。半导体结构包括半导体衬底; 形成在所述半导体衬底中的沟道区; 包括电介质层和导电层并形成在沟道区上方的栅极; 源极和漏极区域形成在栅极的相对侧; 第一浅沟槽隔离物嵌入半导体衬底并具有平行于栅极长度方向的长度方向; 以及第二浅沟槽隔离件，每个隔离件邻接源极或漏极区域的外侧壁并邻接第一浅沟槽隔离物，其中源极和漏极区域包括邻接第二浅沟槽隔离物的第一晶种层和顶部第二浅沟槽隔离物的表面高于或高于源区和漏区的顶表面。

185. 发明申请

US20120001198A1 ISOLATION REGION, SEMICONDUCTOR DEVICE AND METHODS FOR FORMING THE SAME 有权
标题翻译：分离区，半导体器件及其形成方法
公开(公告)号：US20120001198A1
公开(公告)日：2012-01-05
申请号：US13119129
申请日：2011-02-18
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/16 , H01L21/336 , H01L21/31 , H01L29/06 , H01L29/772
CPC分类号： H01L21/3083 , H01L21/76232 , H01L29/66636 , H01L29/78
摘要： An isolation region is provided. The isolation region includes a first groove and an insulation layer filling the first groove. The first groove is embedded into a semiconductor substrate and includes a first sidewall, a bottom surface and a second sidewall that extends from the bottom surface and joins to the first sidewall. An angle between the first sidewall and a normal line of the semiconductor substrate is larger than a standard value. A method for forming an isolation region is further provided. The method includes: forming a first trench on a semiconductor substrate, wherein an angle between a sidewall of the first trench and a normal line of the semiconductor substrate is larger than a standard value; forming a mask on the sidewall to form a second trench on the semiconductor substrate by using the mask; and forming an insulation layer to fill the first and second trenches. A semiconductor device and a method for forming the same are still further provided. In the semiconductor device, a material of the semiconductor substrate is interposed between a second groove bearing a semiconductor layer for forming an S/D region and the first and second sidewalls. The present invention is beneficial to reduce leakage current.
摘要翻译：提供隔离区域。隔离区域包括第一凹槽和填充第一凹槽的绝缘层。第一凹槽被嵌入到半导体衬底中，并且包括从底表面延伸并连接到第一侧壁的第一侧壁，底表面和第二侧壁。半导体衬底的第一侧壁和法线之间的角度大于标准值。还提供了形成隔离区域的方法。该方法包括：在半导体衬底上形成第一沟槽，其中第一沟槽的侧壁和半导体衬底的法线之间的角度大于标准值; 在所述侧壁上形成掩模以通过使用所述掩模在所述半导体衬底上形成第二沟槽; 以及形成绝缘层以填充所述第一和第二沟槽。还提供一种半导体器件及其形成方法。在半导体器件中，半导体衬底的材料插入在用于形成S / D区域的半导体层的第二沟槽和第一和第二侧壁之间。本发明有益于减少漏电流。

186. 发明申请

US20110316088A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US20110316088A1
公开(公告)日：2011-12-29
申请号：US13201827
申请日：2011-02-24
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： A semiconductor structure and a method for forming the same are provided. The structure comprises a semiconductor substrate (100) with an nMOSFET region (102) and a pMOSFET region (104) on it. An nMOSFET structure and a pMOSFET structure are formed in the nMOSFET region (102) and the pMOSFET region (104), respectively. The nMOSFET structure comprises a first channel region (182) formed in the nMOSFET region (102) and a first gate stack formed in the first channel region (182). The nMOSFET structure is covered with a compressive-stressed material layer (130) to apply a tensile stress to the first channel region (182). The pMOSFET structure comprises a second channel region (184) formed in the pMOSFET region (104) and a second gate stack formed in the second channel region (184). The pMOSFET structure is covered with a tensile-stressed material layer (140) to apply a compressive stress to the second channel region (184).
摘要翻译：提供半导体结构及其形成方法。该结构包括其上具有nMOSFET区域（102）和pMOSFET区域（104）的半导体衬底（100）。 nMOSFET结构和pMOSFET结构分别形成在nMOSFET区域（102）和pMOSFET区域（104）中。 nMOSFET结构包括形成在nMOSFET区域（102）中的第一沟道区（182）和形成在第一沟道区（182）中的第一栅叠层。 nMOSFET结构用压应力材料层（130）覆盖，以向第一沟道区域（182）施加拉伸应力。 pMOSFET结构包括形成在pMOSFET区域（104）中的第二沟道区（184）和形成在第二沟道区（184）中的第二栅叠层。 pMOSFET结构被拉伸应力材料层（140）覆盖，以向第二通道区域（184）施加压缩应力。

187. 发明申请

US20110284934A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110284934A1
公开(公告)日：2011-11-24
申请号：US12997766
申请日：2010-09-16
申请人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
发明人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66636 , H01L29/1083 , H01L29/66659 , H01L29/7391 , H01L29/78
摘要： There are provided a semiconductor device and a method of fabricating the same. The semiconductor device comprises: a semiconductor substrate of a first conductive type; a gate formed on the semiconductor substrate; and a heavily doped region of the first conductive type and a heavily doped region of a second conductive type formed respectively in the semiconductor substrate at either side of the gate, wherein the heavily doped region of the second conductive type is separated from the channel region under the gate and partially separated from the semiconductor substrate by a dielectric layer. By means of this semiconductor device, it is possible to provide excellent switching behavior.
摘要翻译：提供了一种半导体器件及其制造方法。半导体器件包括：第一导电类型的半导体衬底; 形成在半导体衬底上的栅极; 以及第一导电类型的重掺杂区域和分别位于栅极两侧的半导体衬底中的第二导电类型的重掺杂区域，其中第二导电类型的重掺杂区域与下面的沟道区域分开并且通过电介质层与半导体衬底部分地分离。通过该半导体器件，可以提供优异的开关行为。

188. 发明申请

US20110272767A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110272767A1
公开(公告)日：2011-11-10
申请号：US12991012
申请日：2010-09-16
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/66575 , H01L21/28079 , H01L21/28088 , H01L21/76897 , H01L23/485 , H01L29/66545
摘要： There is provided a semiconductor device and a method of fabricating the same. The method comprises: providing a semiconductor substrate; forming a transistor structure on the semiconductor substrate, wherein the transistor structure comprises a gate region and a source/drain region, and the gate region comprises a gate dielectric layer provided on the semiconductor substrate and a sacrificial gate formed on the gate dielectric layer; depositing a first interlayer dielectric layer, and planarizing the first interlayer dielectric layer to expose the sacrificial gate; removing the sacrificial gate to form a replacement gate hole; forming first contact holes at positions corresponding to the source/drain region in the first interlayer dielectric layer; and filling a first conductive material in the first contact holes and the replacement gate hole respectively to form first contacts and a replacement gate, wherein the first contacts come into contact with the source/drain region. Thereby, the replacement gate and the first contacts can be made in one same step of depositing the same material, and thus the process flows are simplified.
摘要翻译：提供了一种半导体器件及其制造方法。该方法包括：提供半导体衬底; 在所述半导体衬底上形成晶体管结构，其中所述晶体管结构包括栅极区域和源极/漏极区域，并且所述栅极区域包括设置在所述半导体衬底上的栅极介电层和形成在所述栅极电介质层上的牺牲栅极; 沉积第一层间介电层，平面化第一层间电介质层以暴露牺牲栅极; 去除牺牲栅极以形成替换门孔; 在与所述第一层间电介质层中的所述源极/漏极区对应的位置处形成第一接触孔; 以及分别在所述第一接触孔和所述替换栅极孔中填充第一导电材料以形成第一触点和替换栅极，其中所述第一触点与所述源极/漏极区域接触。因此，可以在沉积相同材料的同一步骤中制造更换栅极和第一触点，从而简化了工艺流程。

189. 发明申请

US20110198676A1 FIN TRANSISTOR STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
标题翻译： FIN晶体管结构及其制造方法
公开(公告)号：US20110198676A1
公开(公告)日：2011-08-18
申请号：US13077858
申请日：2011-03-31
申请人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
发明人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A fin transistor structure and a method of fabricating the same are disclosed. In one aspect the method comprises providing a bulk semiconductor substrate, patterning the semiconductor substrate to form a fin with it body directly tied to the semiconductor substrate, patterning the fin so that gaps are formed on the bottom of the fin at source/drain regions of the transistor structure to be formed. This is performed wherein a portion of the fin corresponding to the channel region of the transistor structure to be formed is directly tied to t he semiconductor substrate, while other portions of the fin at the source/drain regions are separated from the surface of the semiconductor substrate by the gaps. Also, filling an insulation material into the gaps, and fabricating the transistor structure based on the semiconductor substrate with the fin formed thereon are disclosed. Thereby, it is possible to reduce the leakage current while maintaining the advantages of body-tied structures.
摘要翻译：公开了鳍式晶体管结构及其制造方法。在一个方面，该方法包括提供体半导体衬底，图案化半导体衬底以形成鳍片，其主体直接连接到半导体衬底，图案化鳍片，使得在鳍片的底部形成间隙，在源极/漏极区域要形成的晶体管结构。这样进行，其中对应于要形成的晶体管结构的沟道区的鳍的一部分直接与半导体衬底相连，而源极/漏极区的鳍的其它部分与半导体的表面分离基板间隙。此外，公开了将绝缘材料填充到间隙中，并且制造基于其上形成有翅片的半导体衬底的晶体管结构。因此，可以在保持身体结构的优点的同时减小漏电流。

190. 发明授权

US07541629B1 Embedded insulating band for controlling short-channel effect and leakage reduction for DSB process 失效
标题翻译：嵌入式绝缘带，用于控制DSB工艺的短沟道效应和泄漏降低
公开(公告)号：US07541629B1
公开(公告)日：2009-06-02
申请号：US12106658
申请日：2008-04-21
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/72
CPC分类号： H01L29/7848 , H01L29/045 , H01L29/0653 , H01L29/165 , H01L29/66568 , H01L29/66636 , H01L29/78
摘要： A method and structure for reducing leakage currents in integrated circuits based on a direct silicon bonding (DSB) fabrication process. After recessing a top semiconductor layer and an underlying semiconductor substrate, a dielectric layer may be deposited and etched back to form embedded spacers. Conventional source/drain regions may then be formed.
摘要翻译：一种基于直接硅键（DSB）制造工艺减小集成电路漏电流的方法和结构。在凹陷顶部半导体层和下面的半导体衬底之后，可以沉积介电层并回蚀刻以形成嵌入的间隔物。然后可以形成常规的源极/漏极区域。

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