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171. 发明授权

US08423876B2 Low-density parity check convolution code (LDPC-CC) encoder and LDPC-CC decoder 有权
标题翻译：低密度奇偶校验卷积码（LDPC-CC）编码器和LDPC-CC解码器
公开(公告)号：US08423876B2
公开(公告)日：2013-04-16
申请号：US12668655
申请日：2008-07-11
申请人： Shutai Okamura , Yutaka Murakami , Masayuki Orihashi
发明人： Shutai Okamura , Yutaka Murakami , Masayuki Orihashi
IPC分类号： H03M13/03
CPC分类号： H03M13/118 , H03M13/1111 , H03M13/1154 , H03M13/23 , H03M13/235 , H03M13/6362
摘要： It is possible to provide and an LDPC-CC (Low-Density Parity-Check Convolution Codes) encoder and an LDPC-CC decoder which performs an error correction encoding and decoding while reducing the amount of a termination sequence required for encoding/decoding the LDPC-CC encoding/decoding and suppressing degradation of the transmission efficiency. The LDPC-CC encoder (400) includes a weight control unit (470) which stores a weight pattern (475) based on an LDPC-CC inspection matrix (100); and a weight pattern (476) based on a check matrix (300) obtained by deforming an LDPC-CC inspection matrix (100). The weight control unit (470) controls a weight to be multiplied onto the outputs of a plurality of shift registers (410-1 to 410-M, 430-1 to 430-M) by using the weight pattern (475) when the input bit is an information sequence, and using a weight pattern (476) which makes a weight value to be multiplied by an inspection bit v2,t to be 0 when the input bit is a termination sequence.
摘要翻译：可以提供LDPC-CC（低密度奇偶校验卷积码）编码器和LDPC-CC解码器，该LDPC-CC解码器在减少LDPC编码/解码所需的终止序列的量的同时进行纠错编码和解码 -CC编码/解码并抑制传输效率的降低。 LDPC-CC编码器（400）包括：权重控制单元（470），其基于LDPC-CC检查矩阵（100）存储权重模式（475）; 以及基于通过使LDPC-CC检查矩阵（100）变形而获得的校验矩阵（300）的权重模式（476）。权重控制单元（470）通过使用加权模式（475）来控制要乘以多个移位寄存器（410-1至410-M，430-1至430-M）的输出的权重位是信息序列，并且当输入比特是终止序列时，使用使加权值乘以检查比特v2的加权模式（476），t为0。

172. 发明授权

US08422581B2 Multi-antenna transmission device, multi-antenna reception device, multi-antenna transmission method, multi-antenna reception method, terminal device, and base station device 有权
标题翻译：多天线发送装置，多天线接收装置，多天线发送方法，多天线接收方法，终端装置和基站装置
公开(公告)号：US08422581B2
公开(公告)日：2013-04-16
申请号：US12523481
申请日：2008-01-21
申请人： Naoya Yosoku , Yutaka Murakami
发明人： Naoya Yosoku , Yutaka Murakami
IPC分类号： H04B7/02
CPC分类号： H04B7/0689 , H04L1/0003 , H04L1/0009 , H04L1/0026 , H04L5/0023 , H04L25/0224 , H04L25/03343 , H04L27/368 , H04L2025/03426
摘要： Provided is a multi-antenna transmission device (400) which can perform MLD by using a simple configuration of a reception device in a MIMO-AMC system. The multi-antenna transmission device (400) includes common signal point mapping units (401, 402) for mapping data transmitted from different antennas (111, 112) in transmission scheme using MIMO spatial multiplexing, to common signal points shared by respective modulation methods. Thus, the arrangement of baseband signal points obtained by mapping a code word after channel encoding onto an IQ plane can be shared as common signal points shared by modulation methods. Accordingly, the reception device need not prepare a particular circuit for performing MLD calculation in accordance with a combination of the methods for modulating the signals which have been MIMO-space multiplexed. This can reduce the circuit size of the MLD calculation circuit.
摘要翻译：提供一种可以通过使用MIMO-AMC系统中的接收装置的简单配置来执行MLD的多天线发送装置（400）。多天线发送装置（400）包括用于将使用MIMO空间复用的传输方案中的不同天线（111,112）发送的数据映射到由各个调制方式共享的公共信号点的公共信号点映射单元（401,402）。因此，通过将通道编码之后的码字映射到IQ平面上而获得的基带信号点的布置可以被共享为由调制方法共享的公共信号点。因此，接收装置不需要根据用于调制已被MIMO空间多路复用的信号的方法的组合来准备用于执行MLD计算的特定电路。这可以减少MLD计算电路的电路尺寸。

173. 发明授权

US08406346B2 Code error detecting device, wireless system and code error detecting method 有权
标题翻译：代码错误检测装置，无线系统和代码错误检测方法
公开(公告)号：US08406346B2
公开(公告)日：2013-03-26
申请号：US12305570
申请日：2007-06-20
申请人： Kazuaki Takahashi , Suguru Fujita , Michiaki Matsuo , Yutaka Murakami , Satoshi Hasako
发明人： Kazuaki Takahashi , Suguru Fujita , Michiaki Matsuo , Yutaka Murakami , Satoshi Hasako
IPC分类号： H03D3/22 , H04L7/00 , H04B7/208
CPC分类号： H04L27/06 , H04L1/0045 , H04L1/06 , H04L1/1812 , H04L1/1829 , H04L25/03171 , H04L25/067
摘要： A code error detecting device that can more precisely detect a code error due to a delayed wave is disclosed. The code error detecting device includes a receiving antenna (121) for receiving a on-off keying modulated pulse and its code-reversed pulse, a pulse detector (124) for outputting detected data in accordance with the pulses, a code comparing unit (128) for comparing each code of first received data (R1) with one of second received data (R2), wherein the first and second received data are derived from the output detected data, and an error detecting unit (129) for detecting an error of each code from a comparison result (D2) indicative of a result compared in the code comparing unit (128).
摘要翻译：公开了一种可以更精确地检测由于延迟波引起的码错误的码错误检测装置。代码错误检测装置包括用于接收开关键控调制脉冲及其代码反转脉冲的接收天线（121），用于根据脉冲输出检测数据的脉冲检测器（124），代码比较单元（128 ），用于将第一接收数据（R1）的每个代码与第二接收数据（R2）中的一个进行比较，其中从所述输出检测数据导出第一和第二接收数据;以及错误检测单元（129），用于检测来自代码比较单元（128）中比较结果的比较结果（D2）的每个代码。

174. 发明授权

US08401110B2 Transmission method, transmitter apparatus and reception method 有权
标题翻译：传输方法，发射机设备和接收方法
公开(公告)号：US08401110B2
公开(公告)日：2013-03-19
申请号：US12447885
申请日：2007-11-01
申请人： Yutaka Murakami , Shutai Okamura , Kiyotaka Kobayashi , Masayuki Orihashi , Kazuaki Takahashi
发明人： Yutaka Murakami , Shutai Okamura , Kiyotaka Kobayashi , Masayuki Orihashi , Kazuaki Takahashi
IPC分类号： H04L5/12 , H04L23/02
CPC分类号： H04L1/0071 , H03M13/15 , H04L1/0003 , H04L1/0009 , H04L1/0059 , H04L1/22 , H04L5/0007 , H04L27/0008 , H04L27/2647 , H04L27/36 , H04L27/38
摘要： A transmitter apparatus wherein a simple structure is used to successfully suppress the degradation of error rate performance that otherwise would be caused by fading or the like. There are included encoding parts (11—1-11—4) that encode transport data; a mapping part (3304) that performs such a mapping that encoded data sequentially formed by the encoding parts (11—1-11—4) are not successively included in the same symbol, thereby forming data symbols; and a symbol interleaver (3301) that interleaves the data symbols. In this way, a low computational complexity can be used to perform an interleaving process equivalent to a bit interleaving process to effectively improve the reception quality at a receiving end.
摘要翻译：一种发射机装置，其中使用简单的结构来成功地抑制否则将由衰落等引起的误码率性能的降级。包括编码传输数据的编码部分（11-1-11-4）; 执行编码由编码部分（11-1-11-4）顺序形成的数据的映射的映射部分（3304）不被连续地包括在相同的符号中，从而形成数据符号; 以及交错数据符号的符号交织器（3301）。以这种方式，可以使用低的计算复杂度来执行等同于比特交织处理的交织处理，以有效地提高接收端的接收质量。

175. 发明授权

US08286064B2 Transmission device 有权
标题翻译：传输设备
公开(公告)号：US08286064B2
公开(公告)日：2012-10-09
申请号：US12738621
申请日：2008-10-30
申请人： Shutai Okamura , Yutaka Murakami , Naoya Yosoku , Masayuki Orihashi
发明人： Shutai Okamura , Yutaka Murakami , Naoya Yosoku , Masayuki Orihashi
IPC分类号： G06F11/00
CPC分类号： H03M13/1102 , H03M13/23 , H03M13/255 , H03M13/356 , H03M13/373 , H03M13/6362 , H04L1/005 , H04L1/0057 , H04L1/0059 , H04L1/0069 , H04L1/0071 , H04L1/06 , H04L5/0044 , H04L27/2626 , H04L27/3422
摘要： Provided is a transmission device which improves the error rate characteristic upon decoding when performing error correction encoding by using a self-orthogonal code or an LDPC-CC in a communication system using a communication path having a fading fluctuation, multi-value modulation, or MIMO transmission. In the transmission device, the self-orthogonal encoding unit (110) encodes a self-orthogonal code having a constriction length K and an interleave unit (130) rearranges a code word sequence so that the same modulation symbol includes an information bit of a moment i and a non-correlated bit of the information bit of the moment i in a multi-value modulation unit (150).
摘要翻译：提供一种传输装置，其在使用具有衰落波动，多值调制或MIMO的通信路径的通信系统中通过使用自正交码或LDPC-CC进行纠错编码时，提高解码时的错误率特性传输。在发送装置中，自正交编码单元（110）编码具有收缩长度K的自正交码和交织单元（130）重新排列码字序列，使得相同的调制符号包括一个信息位 i和多值调制单元（150）中的时刻i的信息比特的非相关比特。

176. 发明申请

US20120215518A1 STORAGE MEDIUM HAVING STORED THEREIN INFORMATION PROCESSING PROGRAM, INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING SYSTEM 有权
标题翻译：具有存储信息处理程序的存储介质，信息处理装置，信息处理方法和信息处理系统
公开(公告)号：US20120215518A1
公开(公告)日：2012-08-23
申请号：US13402991
申请日：2012-02-23
申请人： Yutaka Murakami , Akio Terui , Minoru Hatamoto
发明人： Yutaka Murakami , Akio Terui , Minoru Hatamoto
IPC分类号： G06F9/455
CPC分类号： G06F9/44547
摘要： A normal mode is a processing mode in which processing based on a first architecture for an information processing method is executed, and a compatible mode is a processing mode in which processing based on a second architecture for another information processing method is executed. In the normal mode, first result data obtained by executing the processing based on the first architecture is inputted to an output section configured to output inputted data to a user. In the compatible mode, second result data obtained by executing the processing based on the second architecture is inputted to the output section, in a manner adapting the second result data to input of the output section.
摘要翻译：正常模式是其中执行基于用于信息处理方法的第一架构的处理的处理模式，并且兼容模式是其中执行基于另一信息处理方法的第二架构的处理的处理模式。在正常模式中，通过执行基于第一架构的处理获得的第一结果数据被输入到被配置为向用户输出输入数据的输出部分。在兼容模式下，通过执行基于第二架构的处理而获得的第二结果数据以使第二结果数据适应输入部的输入的方式输入到输出部。

177. 发明申请

US20110264984A1 ENCODING METHOD, ENCODER AND DECODER 有权
公开(公告)号：US20110264984A1
公开(公告)日：2011-10-27
申请号：US13142212
申请日：2009-12-18
申请人： Yutaka Murakami
发明人： Yutaka Murakami
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/2792 , H03M13/1102 , H03M13/23 , H03M13/235 , H03M13/353 , H03M13/6502 , H03M13/6516 , H04L1/0041
摘要： Disclosed is an encoding method to change an encoding rate of an erasure correcting code, while decreasing a circuit scale of an encoder and a decoder. 12k bit (wherein k represents a natural number) which is an encoding output using LDPC-CC with an encoding rate of ½, and comprises information and parity, is defined as one cycle. From the one cycle, only the information is arranged in the output order of the encoding output to obtain 6k bit information X6i, X6i+1, X6i+2, X6i+3, X6i+4, X6i+5, . . . , X6(i+k−1) X6(i+k−1)+1, X6(i+k−1)+2, X6(i+k−1)+3, X6(i+k−1)+4, and X6(i+k−1)+5. Known information is inserted, in 3k pieces of information (Xj) among the 6k bit information, so that when 3k pieces of mutually different j is divided by 3, there is a remainder of 0 regarding k pieces, there is a remainder of 1 regarding k pieces, and there is a remainder of 2 regarding k pieces, to thereby obtain the parity from the information containing the known information. [Numerical formulas] (Da1+Da2+Da3)X(D)+(Db1+Db2+Db3)P(D)=0 (1-1) (DA1+DA2+DA3)X(D)+(DB1+DB2+DB3)P(D)=0 (1-2) (Da1+Da2+Da3)X(D)+(Dss1+Dss2+Dss3)P(D)=0 (1-3) wherein X(D) is a polynomial expression of the information X; P(D) is a polynomial expression of the parity; a1, a2, a3 are integers (with the proviso that a1≠a2≠a3); b1, b2, b3 are integers (with the proviso that b1≠b2≠b3); A1, A2, A3 are integers (with the proviso that A1≠A2≠A3); B1, B2, B3 are integers (with the proviso that B1≠B2≠B3); a1, a2, a3 are integers (with the proviso that a1≠a2≠a3); ss1, ss2, ss3 are integers (with the proviso that ss1≠ss2≠ss3); and “c % d” represents “a remainder when c is divided by d”.

178. 外观设计

USD644763S1 Light-emitting diode lamp 有权
公开(公告)号：USD644763S1
公开(公告)日：2011-09-06
申请号：US29382717
申请日：2011-01-06
申请人： Yutaka Murakami , Haruhiko Uneo , Kenji Takahashi , Yasushige Tomiyoshi
设计人： Yutaka Murakami , Haruhiko Uneo , Kenji Takahashi , Yasushige Tomiyoshi

179. 外观设计

USD644760S1 Light emitting diode lamp 有权
公开(公告)号：USD644760S1
公开(公告)日：2011-09-06
申请号：US29380088
申请日：2010-11-30
申请人： Yutaka Murakami , Kenji Takahashi , Yasushige Tomiyoshi
设计人： Yutaka Murakami , Kenji Takahashi , Yasushige Tomiyoshi

180. 外观设计

USD643552S1 Portion of a light-emitting diode lamp 有权
公开(公告)号：USD643552S1
公开(公告)日：2011-08-16
申请号：US29386005
申请日：2011-02-23
申请人： Yutaka Murakami , Kenji Takahashi , Yasushige Tomiyoshi
设计人： Yutaka Murakami , Kenji Takahashi , Yasushige Tomiyoshi

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