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161. 发明授权

US07432553B2 Structure and method to optimize strain in CMOSFETs 有权
标题翻译：优化CMOSFET应变的结构和方法
公开(公告)号：US07432553B2
公开(公告)日：2008-10-07
申请号：US10905745
申请日：2005-01-19
申请人： Xiangdong Chen , Haining S. Yang
发明人： Xiangdong Chen , Haining S. Yang
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823842 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N or P) of MOSFET. A strain inducing CA nitride coating having an original full thickness is formed over both the PMOSFETs and the NMOSFETs, wherein the strain inducing coating produces an optimized full strain in one kind of semiconductor device and degrades the performance of the other kind of semiconductor device. The strain inducing CA nitride coating is etched to a reduced thickness over the other kind of semiconductor devices, wherein the reduced thickness of the strain inducing coating relaxes and produces less strain in the other MOSFETs.
摘要翻译：公开了包括PMOSFET和NMOSFETS的应变MOSFET的半导体结构以及制造应变MOSFET的方法，其优化MOSFET中的应变，并且更特别地使MOSFET的一种（P或N）中的应变最大化并且使另一种（N或P）MOSFET的应变。在PMOSFET和NMOSFET两者上形成具有原始全厚度的应变诱导性氮化碳氮化物涂层，其中应变诱导涂层在一种半导体器件中产生优化的全应变，并降低其他种类的半导体器件的性能。诱导氮化钛涂层的应变被蚀刻到比另一种半导体器件更薄的厚度，其中应变诱导涂层的减小的厚度在其它MOSFET中松弛并产生较小的应变。

162. 发明申请

US20080237737A1 OVERLAPPED STRESSED LINERS FOR IMPROVED CONTACTS 失效
标题翻译：用于改进联系人的超重压力衬管
公开(公告)号：US20080237737A1
公开(公告)日：2008-10-02
申请号：US11693254
申请日：2007-03-29
申请人： Xiangdong Chen , Jun Jung Kim , Young Gun Ko , Jae-Eun Park , Haining S. Yang
发明人： Xiangdong Chen , Jun Jung Kim , Young Gun Ko , Jae-Eun Park , Haining S. Yang
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823807 , H01L29/7843
摘要： A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.
摘要翻译：提供一种半导体结构，其包括第一有源半导体区域中的第一半导体器件和第二有源半导体区域中的第二半导体器件。第一电介质衬垫覆盖在第一半导体器件上，并且第二电介质衬垫覆盖在第二半导体器件上，第二电介质衬垫在重叠区域与第一电介质衬垫重叠。第二电介质衬垫具有第一部分，第一部分具有与第二栅极导体的顶点接触的第一厚度和从第二栅极导体的周边边延伸的第二部分，第二部分具有基本上大于第一厚度的第二厚度。第一导电通孔接触第一或第二栅极导体和导电通孔中的至少一个延伸穿过第一和第二电介质衬垫在重叠区域。第二导电通孔可以接触第二半导体器件的源极区域或漏极区域中的至少一个。

163. 发明授权

US07368358B2 Method for producing field effect device that includes epitaxially growing SiGe source/drain regions laterally from a silicon body 有权
标题翻译：用于制造场效应器件的方法，其包括从硅体横向生长SiGe源极/漏极区域
公开(公告)号：US07368358B2
公开(公告)日：2008-05-06
申请号：US11345955
申请日：2006-02-02
申请人： Qiqing C. Ouyang , Xiangdong Chen
发明人： Qiqing C. Ouyang , Xiangdong Chen
IPC分类号： H01L21/20 , H01L21/8238
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/7841
摘要： A structure, and method of fabrication, for high performance field effect devices is disclosed. The MOS structures include a crystalline Si body of one conductivity type, a strained SiGe layer epitaxially grown on the Si body serving as a buried channel for holes, a Si layer epitaxially grown on the SiGe layer serving as a surface channel for electrons, and a source and a drain containing an epitaxially deposited, strained SiGe of opposing conductivity type than the Si body. The SiGe source/drain forms a heterojunction and a metallurgical junction with the Si body that coincide with each other with a tolerance of less than about 10 nm, and preferably less than about 5 nm. The heterostructure source/drain is instrumental in reducing short channel effects. These structures are especially advantageous for PMOS due to increased hole mobility in the compressively strained SiGe channel. Representative embodiments include CMOS structures on bulk and on SOI.
摘要翻译：公开了一种用于高性能场效应器件的结构和制造方法。 MOS结构包括一种导电类型的晶体Si体，在用作空穴的掩埋沟道的Si体上外延生长的应变SiGe层，在用作电子的表面通道的SiGe层上外延生长的Si层，以及源极和漏极，其包含与Si体相反的导电类型的外延沉积的应变SiGe。 SiGe源极/漏极与Si体形成异质结和冶金结，其彼此重合，具有小于约10nm，优选小于约5nm的公差。异质结构源/漏极有助于减少短沟道效应。由于在压缩应变SiGe通道中空穴迁移率增加，这些结构对于PMOS是特别有利的。代表性的实施例包括在本体上和在SOI上的CMOS结构。

164. 发明申请

US20080023752A1 BORON DOPED SiGe HALO FOR NFET TO CONTROL SHORT CHANNEL EFFECT 审中-公开
标题翻译： BORON DOPED SiGe HALO用于NFET控制短路通道效应
公开(公告)号：US20080023752A1
公开(公告)日：2008-01-31
申请号：US11460766
申请日：2006-07-28
申请人： Xiangdong Chen , Yung Fu Chong , Zhijiong Luo , Xinlin Wang , Haining S. Yang
发明人： Xiangdong Chen , Yung Fu Chong , Zhijiong Luo , Xinlin Wang , Haining S. Yang
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/1045 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： An n-type field effect transistor (NFET) and methods of forming a halo for an NFET to control the short channel effect are disclosed. One method includes forming a gate over a silicon substrate; recessing the silicon adjacent to the gate; forming a halo by epitaxially growing boron in-situ doped silicon germanium (SiGe) in the recess; and epitaxially growing silicon over the silicon germanium. Alternatively, the halo can be formed by ion implanting boron into an embedded SiGe region within the silicon substrate. The resulting NFET includes a boron doped SiGe halo embedded within the silicon substrate. The embedded SiGe layer may be a relaxed layer without inserting strain in the channel. The high solid solubility of boron in SiGe and low diffusion rate allows formation of a halo that will maintain the sharp profile, which provides better control of the short channel effect and increasing control over NFET threshold voltage roll-off.
摘要翻译：公开了一种n型场效应晶体管（NFET）和用于形成用于NFET的光晕以控制短沟道效应的方法。一种方法包括在硅衬底上形成栅极; 凹陷与栅极相邻的硅; 通过在凹槽中外延生长硼原位掺杂硅锗（SiGe）来形成卤素; 并在硅锗上外延生长硅。或者，可以通过将硼离子注入到硅衬底内的嵌入的SiGe区域中来形成卤素。所得NFET包括嵌入在硅衬底内的硼掺杂SiGe光晕。嵌入的SiGe层可以是松弛层，而不会在通道中插入应变。硼在SiGe中的高固体溶解度和低扩散速率允许形成将保持尖锐轮廓的光晕，这提供了对短通道效应的更好控制并增加了对NFET阈值电压滚降的控制。

165. 发明申请

US20070269942A1 DUAL STRESS LINER 有权
标题翻译：双应力衬管
公开(公告)号：US20070269942A1
公开(公告)日：2007-11-22
申请号：US11383560
申请日：2006-05-16
申请人： Xiangdong Chen , Haining S. Yang
发明人： Xiangdong Chen , Haining S. Yang
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L29/7842
摘要： A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second source region, a second drain region and a second gate conductor overlying the second channel region. The first and second gate conductors are portions of a single elongated conductive member extending over both the first and second channel regions. A first stressed film overlies the first FET, the first stressed film applying a stress having a first value to the first channel region. A second stressed film overlies the second FET, the second stressed film applying a stress having a second value to the second channel region. The second value is substantially different from the first value. In addition, the first and second stressed films abut each other at a common boundary and present a substantially co-planar major surface at the common boundary.
摘要翻译：提供一种半导体器件结构，其包括第一场效应晶体管（“FET”），其具有第一沟道区，第一源极区，第一漏极区和覆盖第一沟道区的第一栅极导体。包括第二FET，其具有覆盖第二沟道区的第二沟道区，第二源极区，第二漏极区和第二栅极导体。第一和第二栅极导体是在第一和第二沟道区两者上延伸的单个细长导电构件的部分。第一应力膜覆盖第一FET，第一应力膜将具有第一值的应力施加到第一沟道区。第二应力膜覆盖第二FET，第二应力膜向第二沟道区施加具有第二值的应力。第二个值与第一个值大不相同。此外，第一和第二应力膜在共同边界处彼此邻接并且在共同边界处呈现基本上共平面的主表面。

166. 发明授权

US07057216B2 High mobility heterojunction complementary field effect transistors and methods thereof 有权
标题翻译：高迁移率异质结互补场效应晶体管及其方法
公开(公告)号：US07057216B2
公开(公告)日：2006-06-06
申请号：US10698122
申请日：2003-10-31
申请人： Qiqing Christine Ouyang , Xiangdong Chen
发明人： Qiqing Christine Ouyang , Xiangdong Chen
IPC分类号： H01L29/778
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/7841
摘要： In all representative embodiments presented, the Ge concentration in the source and drain 10 and the SiGe epitaxial channel layer 20 is in the 15% to 50% range, preferably between about 20% to 40%. The SiGe thicknesses in the source/drain 10 are staying below the critical thickness for the given Ge concentration. The critical thickness is defined such that above it the SiGe will relax and defects and dislocations will form. The thickness of the SiGe epitaxial layer 20 typically is between about 5nm and 15nm. The thickness of the epitaxial Si layer 30 is typically between about 5nm and 15nm. FIG. 1A shows an embodiment where the body is bulk Si. These type of devices are the most common devices in present day microelectronics. FIGS. 1B and 1C show representative embodiment of the heterojunction source/drain FET device when the Si body 40 is disposed on top of an insulating material 55. This type of technology is commonly referred to as silicon on insulator (SOI) technology. The insulator material 55 usually, and preferably, is SiO2. FIG. 1B shows an SOI embodiment where the body 40 has enough volume to contain mobile charges. Such SOI devices are called partially depleted devices. FIG. 1C shows an SOI embodiment where the volume of the body 40 is insufficient to contain mobile charges. Such SOI devices are called fully depleted devices. For devices shown in FIG. 1B and 1C there is, at least a thin, layer of body underneath the source and drain 10. This body material serves as the seed material onto which the epitaxial SiGe source and drain 10 are grown. In an alternate embodiment, shown in FIG. 1D. for extremely thin fully depleted SOI devices, one could grow the source and drain 10 laterally, from a lateral seeding, in which case the source and drain 10 would penetrate all the way down to the insulating layer 55.
摘要翻译：公开了一种用于高性能场效应装置的结构和制造方法。 MOS结构包括一个导电类型的晶体Si体，在作为空穴的掩埋沟道的Si体上外延生长的外延生长的SiGe层，在用作电子的表面通道的SiGe层上外延生长的Si层，以及漏极含有与Si体相反的导电类型的外延沉积的应变SiGe。 SiGe源极/漏极与Si体形成异质结和冶金结，它们彼此重合，其公差小于约10nm，优选小于约5nm。异质结构源/漏极有助于减少短沟道效应。由于在压缩应变的SiGe沟道中增加的空穴迁移率，这些结构对于PMOS是特别有利的。代表性的实施例包括大块和SOI上的CMOS结构。

167. 发明授权

US09293584B2 FinFET devices 有权
标题翻译： FinFET器件
公开(公告)号：US09293584B2
公开(公告)日：2016-03-22
申请号：US13287331
申请日：2011-11-02
申请人： Xiangdong Chen , Henry Chen , Agnes Woo , Wei Xia
发明人： Xiangdong Chen , Henry Chen , Agnes Woo , Wei Xia
IPC分类号： H01L29/78 , H01L29/66 , H01L29/94 , H01L49/02
CPC分类号： H01L29/785 , H01L28/20 , H01L29/66795 , H01L29/7855 , H01L29/7856 , H01L29/94
摘要： Disclosed are various embodiments of FinFET semiconductor devices. A pair of matched capacitors can be formed that share a common source, drain and/or channel. Accordingly, the capacitance characteristics of each capacitor can be manufactured such that they are similar to one another. A resistor manufactured by employing FinFET techniques is also described. The resistor can be manufactured with an effective length that is greater than a distance traversed along a substrate by the resistor.
摘要翻译：公开了FinFET半导体器件的各种实施例。可以形成一对共用的源极，漏极和/或沟道的匹配电容器。因此，可以制造每个电容器的电容特性使得它们彼此相似。还描述了采用FinFET技术制造的电阻器。电阻器可以制造成有效长度大于通过电阻器沿衬底穿过的距离。

168. 发明授权

US09275976B2 System-in-package with integrated socket 有权
标题翻译：带集成插座的系统级封装
公开(公告)号：US09275976B2
公开(公告)日：2016-03-01
申请号：US13405207
申请日：2012-02-24
申请人： Sam Ziqun Zhao , Kevin Kunzhong Hu , Sampath K. V. Karikalan , Rezaur Rahman Khan , Pieter Vorenkamp , Xiangdong Chen
发明人： Sam Ziqun Zhao , Kevin Kunzhong Hu , Sampath K. V. Karikalan , Rezaur Rahman Khan , Pieter Vorenkamp , Xiangdong Chen
IPC分类号： H01L23/552 , H01L25/065
CPC分类号： H01L25/0657 , H01L23/552 , H01L2224/1403 , H01L2224/14181 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/73253 , H01L2225/06517 , H01L2225/06537 , H01L2225/06572 , H01L2225/06589
摘要： There are disclosed herein various implementations of a system-in-package with integrated socket. In one such implementation, the system-in-package includes a first active die having a first plurality of electrical connectors on a top surface of the first active die, an interposer situated over the first active die, and a second active die having a second plurality of electrical connectors on a bottom surface of the second active die. The interposer is configured to selectively couple at least one of the first plurality of electrical connectors to at least one of the second plurality of electrical connectors. In addition, a socket encloses the first and second active dies and the interposer, the socket being electrically coupled to at least one of the first active die, the second active die, and the interposer.
摘要翻译：这里公开了具有集成插座的系统级封装的各种实施方式。在一个这样的实现中，系统级封装包括第一有源裸片，其具有在第一有源裸片的顶表面上的第一多个电连接器，位于第一有源裸片上的中介层，以及具有第二激活裸片的第二激活裸片多个电连接器在第二有源管芯的底表面上。插入器被配置为选择性地将第一多个电连接器中的至少一个耦合到第二多个电连接器中的至少一个。此外，插座包围第一和第二有源裸片和插入器，插座电耦合到第一有源裸片，第二激活裸片和插入器中的至少一个。

169. 发明授权

US09165834B2 Integrated native device without a halo implanted channel region and method for its fabrication 有权
标题翻译：没有光晕注入通道区域的集成本机器件及其制造方法
公开(公告)号：US09165834B2
公开(公告)日：2015-10-20
申请号：US12660618
申请日：2010-03-01
申请人： Xiangdong Chen , Akira Ito
发明人： Xiangdong Chen , Akira Ito
IPC分类号： H01L29/66 , H01L21/8234 , H01L21/265 , H01L29/10
CPC分类号： H01L21/823412 , H01L21/26586 , H01L29/1083
摘要： According to one embodiment, a semiconductor structure including an integrated native device without a halo implanted channel region comprises an arrangement of semiconductor devices formed over a common substrate, the arrangement includes native devices disposed substantially perpendicular to non-native devices, wherein each of the native and non-native devices includes a respective channel region. The arrangement is configured to prevent formation of halo implants in the native device channel regions during halo implantation of the non-native device channel regions. In one embodiment, the disclosed native devices comprise native transistors capable of avoiding threshold voltage roll-up for channel lengths less than approximately 0.5 um.
摘要翻译：根据一个实施例，包括没有晕圈注入沟道区的集成本机器件的半导体结构包括形成在公共衬底上的半导体器件的布置，该布置包括基本上垂直于非本地器件设置的天然器件，其中每个天线非本地设备包括相应的信道区域。该配置被配置为在非天然器件沟道区域的晕圈植入期间防止在天然器件沟道区域中形成晕轮植入物。在一个实施例中，所公开的天线装置包括天线晶体管，其能够避免小于约0.5μm的信道长度的阈值电压累加。

170. 发明授权

US09059179B2 Semiconductor package with a bridge interposer 有权
标题翻译：具有桥插入器的半导体封装
公开(公告)号：US09059179B2
公开(公告)日：2015-06-16
申请号：US13339266
申请日：2011-12-28
申请人： Sampath K. V. Karikalan , Sam Ziqun Zhao , Kevin Kunzhong Hu , Rezaur Rahman Khan , Pieter Vorenkamp , Xiangdong Chen
发明人： Sampath K. V. Karikalan , Sam Ziqun Zhao , Kevin Kunzhong Hu , Rezaur Rahman Khan , Pieter Vorenkamp , Xiangdong Chen
IPC分类号： H01L23/48 , H01L23/538
CPC分类号： H01L25/0655 , H01L23/48 , H01L23/49827 , H01L23/49833 , H01L23/538 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/80 , H01L24/82 , H01L25/0652 , H01L2224/0401 , H01L2224/05541 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/1703 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73215 , H01L2224/73265 , H01L2224/96 , H01L2924/00014 , H01L2924/15192 , H01L2924/152 , H01L2924/1532 , H01L2924/30105 , H01L2924/00012 , H01L2924/014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs).
摘要翻译：这里公开了包括桥插入器的半导体封装的各种实施方式。一个示例性实现包括具有位于桥插入件上方的第一部分的第一有源管芯和不位于桥插入件上的第二部分。半导体封装还包括具有位于桥插入件上方的第一部分的第二有源管芯和不位于桥插入件上的第二部分。第一有源裸片的第二部分和第二有源裸片的第二部分包括安装在封装衬底上的焊球，并且被配置为使用焊球将电信号传送到封装衬底，并且不使用贯穿半导体通孔（TSV ）。

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