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151. 发明授权

US07825698B2 Method and apparatus for systematic and random variation and mismatch compensation for multilevel flash memory operation 有权
标题翻译：用于多级闪存操作的系统和随机变化和失配补偿的方法和装置
公开(公告)号：US07825698B2
公开(公告)日：2010-11-02
申请号：US12131008
申请日：2008-05-30
申请人： Hieu Van Tran , Hung Quoc Nguyen
发明人： Hieu Van Tran , Hung Quoc Nguyen
IPC分类号： G01R19/00
CPC分类号： G11C16/28 , G11C7/02 , G11C7/062 , G11C7/08 , G11C11/5642 , G11C16/30
摘要： Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing transistor. For an NMOS sensing transistor, a triple well is used with the variable bulk voltage. Differential sense amplifiers with various offset compensation are included. Intentional offset creation for useful purpose is also included.
摘要翻译：公开了用于存储器感测系统的随机或系统失配补偿的方法和装置。感测放大器包括用于将感测晶体管的体积设置为不同于驱动感测晶体管的电压的电压的体电压源。对于NMOS感测晶体管，使用三重阱作为可变体电压。包括各种偏移补偿的差分放大器。有意义的意图偏移创建也包括在内。

152. 发明申请

US20100226181A1 Array Of Non-volatile Memory Cells Including Embedded Local And Global Reference Cells And System 有权
公开(公告)号：US20100226181A1
公开(公告)日：2010-09-09
申请号：US12398155
申请日：2009-03-04
申请人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
发明人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C5/025 , G11C7/14 , G11C16/30 , H01L27/11521 , H01L29/42328 , H01L29/7881
摘要： A non-volatile memory device comprises an array of non-volatile memory cells arranged in a plurality of rows and columns. Each memory cell has a bit terminal for connection to a bit line, a high voltage terminal for connection to a high voltage source, and a low voltage terminal for connection to a low voltage source. The array has a first side adjacent to a first column of memory cells, and a second side opposite the first side, a third side adjacent to a first row of memory cells, and a fourth side opposite the third side. The memory device further comprises a plurality of columns of reference memory cells embedded in the memory array, with a plurality of reference cells in each row of the array of non-volatile memory cells, substantially evenly spaced apart from one another. Each of the reference memory cells is substantially the same as the non-volatile memory cells, and has a bit terminal for connection to a bit line, a high voltage terminal for connection to a high voltage source and a low voltage terminal for connection to a low voltage source. A high voltage decoder is positioned on the first side, and has a plurality of high voltage lines, with each high voltage line connected to the high voltage terminal of the memory cells and reference cells in the same row. A low voltage row decoder is positioned on the second side, and has a plurality of low voltage lines, with each low voltage line connected to the low voltage terminal of the memory cells and reference cells in the same row. A plurality of sense amplifiers are positioned on the third side, with each sense amplifier connected to the bit terminal of one column of non-volatile memory cells and to the bit terminal of a column of reference memory cells. This invention also includes N-of-M selective reference scheme, distributed source line pull down, source line resistance strap compensation, replica-data-pattern current consumption, data current compensation, and bit line voltage error compensation.

153. 发明授权

US07778080B2 Flash memory array system including a top gate memory cell 有权
公开(公告)号：US07778080B2
公开(公告)日：2010-08-17
申请号：US12200930
申请日：2008-08-28
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/34
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

154. 发明授权

US07697365B2 Sub volt flash memory system 有权
标题翻译：亚伏闪存系统
公开(公告)号：US07697365B2
公开(公告)日：2010-04-13
申请号：US11777895
申请日：2007-07-13
申请人： Hieu Van Tran , Sang T Nguyen , Anh Ly , Hung Q. Nguyen
发明人： Hieu Van Tran , Sang T Nguyen , Anh Ly , Hung Q. Nguyen
IPC分类号： G11C8/00
CPC分类号： G11C16/28 , G11C16/08 , G11C16/30
摘要： Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.
摘要翻译：各种电路包括具有用于接收不同于电源电压和接地的体电压的体电压端子的MOS晶体管。可以选择性地设置体电压，使得一些MOS晶体管具有设置为电源电压或地的体电压，并且其它MOS晶体管具有不同的体电压。体电压可以设置为MOS晶体管中的正向或反向偏置pn结。各种电路包括比较器，运算放大器，感测电路，解码电路和其它电路。电路可以包括在存储器系统中。

155. 发明授权

US07660161B2 Integrated flash memory systems and methods for load compensation 有权
标题翻译：集成闪存系统和负载补偿方法
公开(公告)号：US07660161B2
公开(公告)日：2010-02-09
申请号：US11655901
申请日：2007-01-19
申请人： Hieu Van Tran
发明人： Hieu Van Tran
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage. In certain aspects, a compensation circuit may employ an operational amplifier configured as a voltage follower. The voltage follower compensates for any variations in supply voltage, forcing a constant voltage drop across the load element(s), thus maintaining a constant load. Other circuits may also be included, such as precharge circuits, clamp circuits, buffer circuits, trimming circuit, and sense amplifier circuits with sensed body effect. System-On-Chip integrated system aspects may include a microcontroller, a mixed IP, and a flash memory system having functionality and blocks that interface and interoperate with each other for load compensation.
摘要翻译：公开了系统和方法，其包括补偿存储器阵列中使用的电源电压的幅度变化的特征。根据一些方面，补偿电路可以为数据列提供可调谐的限流负载，其中可以调整负载来动态补偿电源电压的变化。在某些方面，补偿电路可以采用配置为电压跟随器的运算放大器。电压跟随器补偿电源电压的任何变化，迫使负载元件上的恒定电压降，从而保持恒定的负载。还可以包括其他电路，例如预充电电路，钳位电路，缓冲电路，微调电路，以及感测体效应的读出放大器电路。片上系统集成系统方面可以包括微控制器，混合IP和闪存系统，其具有彼此接口和互操作以进行负载补偿的功能和块。

156. 发明申请

US20100001765A1 SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING 有权
标题翻译：用于低电压高速感应的感应放大器
公开(公告)号：US20100001765A1
公开(公告)日：2010-01-07
申请号：US12493240
申请日：2009-06-28
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： H03F3/45 , G01R19/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译：存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。比较器的第一输入耦合到低阻抗电路和参考电压节点。比较器的第二输入耦合到数据电压节点。第一负载电路加载耦合到参考电压节点的参考电池。第二负载电路加载耦合到数据电压节点的数据单元。

157. 发明申请

US20080290931A1 Charge pump systems and methods 有权
标题翻译：电荷泵系统和方法
公开(公告)号：US20080290931A1
公开(公告)日：2008-11-27
申请号：US11805765
申请日：2007-05-23
申请人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
发明人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
IPC分类号： G05F1/10
CPC分类号： G05F3/02 , H02M3/073 , H02M2001/322
摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.
摘要翻译：数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。电荷泵可以包括多个泵级。示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲，预充电电路。

158. 发明申请

US20080175062A1 Integrated flash memory systems and methods for load compensation 有权
标题翻译：集成闪存系统和负载补偿方法
公开(公告)号：US20080175062A1
公开(公告)日：2008-07-24
申请号：US11655901
申请日：2007-01-19
申请人： Hieu Van Tran
发明人： Hieu Van Tran
IPC分类号： G11C16/26
CPC分类号： G11C16/26
摘要： Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage. In certain aspects, a compensation circuit may employ an operational amplifier configured as a voltage follower. The voltage follower compensates for any variations in supply voltage, forcing a constant voltage drop across the load element(s), thus maintaining a constant load. Other circuits may also be included, such as precharge circuits, clamp circuits, buffer circuits, trimming circuit, and sense amplifier circuits with sensed body effect. System-On-Chip integrated system aspects may include a microcontroller, a mixed IP, and a flash memory system having functionality and blocks that interface and interoperate with each other for load compensation.
摘要翻译：公开了系统和方法，其包括补偿存储器阵列中使用的电源电压的幅度变化的特征。根据一些方面，补偿电路可以为数据列提供可调谐的限流负载，其中可以调整负载来动态补偿电源电压的变化。在某些方面，补偿电路可以采用配置为电压跟随器的运算放大器。电压跟随器补偿电源电压的任何变化，迫使负载元件上的恒定电压降，从而保持恒定的负载。还可以包括其他电路，例如预充电电路，钳位电路，缓冲电路，微调电路，以及感测体效应的读出放大器电路。片上系统集成系统方面可以包括微控制器，混合IP和闪存系统，其具有彼此接口和互操作以进行负载补偿的功能和块。

159. 发明授权

US07116088B2 High voltage shunt regulator for flash memory 有权
标题翻译：闪存高压分流调节器
公开(公告)号：US07116088B2
公开(公告)日：2006-10-03
申请号：US10457975
申请日：2003-06-09
申请人： Hieu Van Tran , Thuan T. Vu , Susmita Karmakar
发明人： Hieu Van Tran , Thuan T. Vu , Susmita Karmakar
IPC分类号： G05F1/40 , H02M3/18
CPC分类号： G05F3/30
摘要： A high shunt regulator provides precise voltage over process, temperature, power supply, and foundries. The HV level is settable by a digital control bits such as fuse bits. A filter network filters out the ripple noise and charge transient. A tracking capacitor divider network speeds up response time. A fractional band gap reference provides fractional bandgap voltage and current, and operates at low power supply and has superior power supply rejection. It is unsusceptible to substrate hot carrier effect. It exposes very little to drain induced barrier lowering effect. The bandgap core has better than conventional transient response and stability. One embodiment has adjustable level control. Complementary TC (temperature coefficient) trimming allows efficient realization of zero temperature coefficients of current and voltage. Higher order curvature correction of voltage and current is integrated. Replica bias for the control loop is presented. A Binary and Approximation Complementary TC search trimming is described. A zero TC fractional voltage less than the theoretical bandgap voltage (
摘要翻译：高分流稳压器提供精确的过程电压，温度，电源和铸造厂。 HV电平可由诸如保险丝位之类的数字控制位来设置。滤波器网络滤除纹波噪声和充电瞬变。跟踪电容分压网络可加快响应时间。分数带隙参考提供分数带隙电压和电流，并且在低电源下工作并具有优异的电源抑制。衬底热载体效应是不可察觉的。它暴露出很少的漏极引起的屏障降低效果。带隙核优于传统的瞬态响应和稳定性。一个实施例具有可调节的电平控制。互补TC（温度系数）修整可以有效地实现电流和电压的零温度系数。整合电压和电流的高阶曲率校正。提出了控制回路的复制偏差。描述了二进制和近似互补TC搜索修剪。小于理论带隙电压（<<〜1.2伏特）的零TC分数电压是可实现的。带隙芯具有抑制高频噪声的滤波机制。低功率启动电路加电带隙。带隙也具有可变阻抗。

160. 发明授权

US07038960B2 High speed and high precision sensing for digital multilevel non-volatile memory system 有权
标题翻译：数字多级非易失性存储器系统的高速和高精度感测
公开(公告)号：US07038960B2
公开(公告)日：2006-05-02
申请号：US10241442
申请日：2002-09-10
申请人： Hieu Van Tran , Jack Edward Frayer , William John Saiki , Michael Stephen Briner
发明人： Hieu Van Tran , Jack Edward Frayer , William John Saiki , Michael Stephen Briner
IPC分类号： G11C7/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C16/28
摘要： A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.
摘要翻译：数字多电平非易失性存储器包括大量感测系统，其包括布置在存储器单元的相邻子阵列上的多个读出放大器。读出放大器包括高速负载，宽输出范围中间级和低阻抗输出驱动器。高速负载提供高速感应。宽输出范围在比较节点上提供高速的感测余量。低阻抗输出驱动器驱动差分比较器的高噪声负载。耦合到读出放大器的输入和输出的预充电电路增加了感测速度。差分比较器具有包括模拟引导的架构。参考读出放大器具有与差分放大器相同的结构，以减少偏移误差。参考差分放大器还包括用于检测冗余单元和参考单元的内容的信号复用。

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