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151. 发明申请

US20050230831A1 Structure to improve adhesion between top CVD low-k dielectiric and dielectric capping layer 有权
标题翻译：结构以改善顶部CVD低k介电层和介电顶盖层之间的粘附
公开(公告)号：US20050230831A1
公开(公告)日：2005-10-20
申请号：US10827693
申请日：2004-04-19
申请人： Lawrence Clevenger , Stefanie Chiras , Timothy Dalton , James Demarest , Derren Dunn , Chester Dziobkowski , Philip Flaitz , Michael Lane , James Lloyd , Darryl Restaino , Thomas Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence Clevenger , Stefanie Chiras , Timothy Dalton , James Demarest , Derren Dunn , Chester Dziobkowski , Philip Flaitz , Michael Lane , James Lloyd , Darryl Restaino , Thomas Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L21/312 , H01L21/316 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/532
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

152. 发明申请

US20050077628A1 Dual damascene structure and method 有权
公开(公告)号：US20050077628A1
公开(公告)日：2005-04-14
申请号：US10684952
申请日：2003-10-14
申请人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
发明人： Kaushik Kumar , Timothy Dalton , Larry Clevenger , Andy Cowley , Douglas La Tulipe , Mark Hoinkis , Chih-Chao Yang , Yi-Hsiung Lin , Erdem Kaltalioglu , Markus Naujok , Jochen Schacht
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

153. 发明授权

US5744734A Fabrication process for high temperature aluminum alloys by squeeze casting 失效
标题翻译：挤压铸造高温铝合金加工工艺
公开(公告)号：US5744734A
公开(公告)日：1998-04-28
申请号：US551110
申请日：1995-10-31
申请人： Chih-Chao Yang , Edward Chang
发明人： Chih-Chao Yang , Edward Chang
IPC分类号： B22F3/26 , B22F9/08 , C22C21/00
CPC分类号： B22F3/26 , Y10T428/12021
摘要： A method for fabricating articles of high-temperature aluminum alloys having a compressional strength of at least 20 kg/mm.sup.2 at temperatures of 300.degree. C. or greater, is disclosed. The method comprises the steps of: (a) forming a porous preform from particles of a first aluminum alloy via cold-pressing, the preform having the shape and dimension of the aluminum alloy article to be fabricated; (b) squeeze-casting a molten second aluminum alloy into void spaces of the porous preform to form an aluminum composite containing the first aluminum alloy, which serves as a reinforcement phase, dispersed in the second aluminum alloy, which serves as a matrix phase; (c) wherein the molten second aluminum alloy is cast at such temperatures so as to cause a surface of the first aluminum alloy particles to melt and thereby form a strong bonding with the second aluminum alloy. The first aluminum alloy particles are formed by melt-spinning, followed by rapid solidification and precipitation, of a composition of the first aluminum alloy to form a thin ribbon, then pulverizing the thin ribbon into particles. Unlike the prior art processes, which fabricate high-temperature aluminum alloys only in essentially two-dimensional articles, the method disclosed herein allows the capability of near net shaping, i.e., it can fabricate high-temperature aluminum alloy articles of essentially any intended shapes. The present process allows selective reinforcement of the fabricated articles to be achieved at strategically important locations, so as to expand the range of engineering applications of the fabricated articles without incurring substantially increased manufacturing cost.
摘要翻译：公开了一种在300℃或更高的温度下制造具有至少20kg / mm 2的压缩强度的高温铝合金制品的方法。该方法包括以下步骤：（a）通过冷压从第一铝合金的颗粒形成多孔预成型件，预制件具有要制造的铝合金制品的形状和尺寸; （b）将熔融的第二铝合金挤压成多孔预型体的空隙空间，形成含有分散在作为基体相的第二铝合金中作为增强相的第一铝合金的铝复合材料; （c）其中熔融的第二铝合金在这样的温度下铸造，使得第一铝合金颗粒的表面熔化，从而与第二铝合金形成牢固的结合。首先通过熔融纺丝形成第一铝合金颗粒，随后快速凝固和沉淀出第一铝合金的组成，形成薄带，然后将薄带粉碎成颗粒。与仅在基本上二维制品中制造高温铝合金的现有技术方法不同，本文公开的方法允许近净成形的能力，即它可以制造基本上任何预期形状的高温铝合金制品。本方法允许选择性地加强要在战略重要位置实现的制造制品，从而扩大制造制品的工程应用范围，而不会导致显着增加的制造成本。

154. 发明授权

US09620619B2 Borderless contact structure 有权
公开(公告)号：US09620619B2
公开(公告)日：2017-04-11
申请号：US13348894
申请日：2012-01-12
申请人： Veeraraghavan S. Basker , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Veeraraghavan S. Basker , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/20 , H01L29/78 , H01L29/66 , H01L21/768 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/76897 , H01L29/66628 , H01L29/78
摘要： A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.

155. 发明授权

US09059254B2 Overlay-tolerant via mask and reactive ion etch (RIE) technique 有权
标题翻译：覆盖层通过掩模和反应离子蚀刻（RIE）技术
公开(公告)号：US09059254B2
公开(公告)日：2015-06-16
申请号：US13604660
申请日：2012-09-06
申请人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/44 , H01L21/768 , H01L21/311
CPC分类号： H01L23/528 , H01L21/31144 , H01L21/76807 , H01L21/76816 , H01L21/76831 , H01L23/5226 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.
摘要翻译：提供了一种方法，其包括首先根据第一掩模蚀刻衬底。第一蚀刻在衬底中形成第一深度的第一蚀刻特征。第一蚀刻还在衬底中形成条条开口。然后可以用填充材料填充条子开口。可以通过去除第一掩模的一部分来形成第二掩模。可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。第二蚀刻将第一蚀刻特征扩展到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。

156. 发明授权

US08957519B2 Structure and metallization process for advanced technology nodes 有权
标题翻译：先进技术节点的结构和金属化过程
公开(公告)号：US08957519B2
公开(公告)日：2015-02-17
申请号：US12910075
申请日：2010-10-22
申请人： Chih-Chao Yang , Hsueh-Chung Chen
发明人： Chih-Chao Yang , Hsueh-Chung Chen
IPC分类号： H01L23/48 , H01L21/321 , H01L21/02 , H01L21/768
CPC分类号： H01L21/321 , H01L21/02304 , H01L21/76852 , H01L21/76886
摘要： The problem of poor adherence of a dielectric coating on a patterned metal structure can be solved by forming an adhesion layer on exposed surfaces of such metal structure prior to deposition of such dielectric. According to an embodiment, the invention provides a method to form a self-aligned adhesion layer on the surface of metal interconnect structure within an integrated circuit by exposing the metal structure to a controlled atmosphere and a flow of nitrogen-containing gas.
摘要翻译：可以通过在沉积这种电介质之前在这种金属结构的暴露表面上形成粘合层来解决图案化金属结构上的电介质涂层粘附性差的问题。根据一个实施例，本发明提供了一种通过将金属结构暴露于受控气氛和含氮气体的流动来在集成电路内的金属互连结构的表面上形成自对准粘附层的方法。

157. 发明授权

US08889546B2 Discontinuous/non-uniform metal cap structure and process for interconnect integration 有权
标题翻译：不连续/不均匀的金属帽结构和互连整合的过程
公开(公告)号：US08889546B2
公开(公告)日：2014-11-18
申请号：US13600773
申请日：2012-08-31
申请人： Chih-Chao Yang , Lynne M. Gignac , Chao-Kun Hu , Surbhi Mittal
发明人： Chih-Chao Yang , Lynne M. Gignac , Chao-Kun Hu , Surbhi Mittal
IPC分类号： H01L21/4763 , H01L23/532 , H01L23/528 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/02362 , H01L21/76849 , H01L21/76865 , H01L21/76868 , H01L23/5283 , H01L23/53223 , H01L23/53252 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material; and forming a noble metal-containing cap directly on the upper surface of the at least one conductive material, wherein the noble metal cap is discontinuous or non-uniform.
摘要翻译：提供一种制造互连结构的方法，其包括提供具有约3.0或更小介电常数的介电材料和嵌入其中的至少一种导电材料，所述至少一种导电材料具有与上表面共面的上表面的介电材料; 并且在所述至少一种导电材料的上表面上直接形成含贵金属的帽，其中所述贵金属帽是不连续的或不均匀的。

158. 发明授权

US08753927B2 Low cost anti-fuse structure and method to make same 失效
标题翻译：低成本的反熔丝结构和方法制作相同
公开(公告)号：US08753927B2
公开(公告)日：2014-06-17
申请号：US13587560
申请日：2012-08-16
申请人： Chih-Chao Yang , Stephen M. Gates
发明人： Chih-Chao Yang , Stephen M. Gates
IPC分类号： H01L21/82
CPC分类号： H01L23/5252 , G11C17/165 , H01L21/7684 , H01L21/76877 , H01L21/76882 , H01L21/76883 , H01L23/5226 , H01L23/5283 , H01L23/53214 , H01L23/53219 , H01L23/53228 , H01L23/53233 , H01L23/53247 , H01L23/5329 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure.
摘要翻译：提供一种抗熔丝结构，其中抗熔丝材料衬垫嵌入设置在互连电介质材料内的一个开口内。反熔丝材料衬垫位于第一导电金属和第二导电金属之间，第一导电金属和第二导电金属也存在于开口内。扩散阻挡衬里将第一导电金属与互连电介质材料的任何部分分开。反熔丝结构横向邻近形成在与反熔丝结构相同的互连电介质材料内的互连结构。

159. 发明授权

US08735279B2 Air-dielectric for subtractive etch line and via metallization 有权
标题翻译：用于减法蚀刻线和通孔金属化的空气电介质
公开(公告)号：US08735279B2
公开(公告)日：2014-05-27
申请号：US13013108
申请日：2011-01-25
申请人： David V Horak , Elbert Huang , Charles W Koburger , Shom Ponoth , Chih-Chao Yang
发明人： David V Horak , Elbert Huang , Charles W Koburger , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L23/522 , H01L21/76802 , H01L21/7682 , H01L21/76885 , H01L21/76897 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.
摘要翻译：公开了一种方法和结构，其中可以形成具有位于最容易受电容耦合的区域中的有效气隙的多个互连层。该方法包括提供导电特征层，所述层包括设置在基底上并彼此隔开小于或等于有效距离的至少两个线构件，以及至少一个这样的线构件，其还具有延伸的通孔构件离开基板，沉积不良共形介电涂层以在这些线构件之间形成气隙，并露出通孔的顶端。

160. 发明授权

US08704343B2 Borderless interconnect line structure self-aligned to upper and lower level contact vias 有权
标题翻译：无边界互连线结构自对准到上层和下层接触孔
公开(公告)号：US08704343B2
公开(公告)日：2014-04-22
申请号：US13607677
申请日：2012-09-08
申请人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
发明人： Shom Ponoth , David V. Horak , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L21/44
CPC分类号： H01L23/528 , H01L21/76885 , H01L21/76897 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.
摘要翻译：金属层沉积在其上暴露下面的金属通孔的顶表面的平坦表面上。图案化金属层以形成至少一个金属块，其具有要形成的金属线的水平横截面积和要形成的至少一个上覆的金属通孔。下面的金属通孔的每个上部凹陷在位于正上方的金属块的区域的外部。至少一个金属块的上部被光刻地图案化以形成集成线和通孔结构，其包括具有基本上恒定的宽度的金属线和至少一个覆盖的金属通孔，其具有相同的基本上恒定的宽度并且与金属线无边界地对准。沉积和平坦化上层电介质材料层，使得至少一个上覆金属通孔的顶表面被暴露。

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