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141. 发明申请

US20140136913A1 DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS 有权
标题翻译：双模式测试访问端口方法和设备
公开(公告)号：US20140136913A1
公开(公告)日：2014-05-15
申请号：US14160163
申请日：2014-01-21
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3185
CPC分类号： G01R31/3177 , G01R31/3172 , G01R31/318536 , G01R31/318555 , G01R31/318572 , G06F1/10
摘要： Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead.
摘要翻译：连接电路将扫描测试端口（STP）电路耦合到测试访问端口（TAP）电路。连接电路具有连接到扫描电路的输入，控制来自TAP电路的输出引线，选择输入引线和时钟输入引线。连接电路具有连接到STP电路的扫描使能（SE）输入引线，捕捉选择（CS）输入引线和扫描时钟（CK）输入引线的输出。连接电路包括多路复用器，其具有与来自TAP电路的时钟选择引线连接的控制输入，与功能时钟引线连接的输入，与时钟输入引线连接的输入，与来自 TAP电路，OFF引线和与扫描时钟输入引线相连的输出。

142. 发明授权

US08707116B2 Transitioning a state machine through idle, sequence, and unlock states 有权
标题翻译：通过空闲，顺序和解锁状态转换状态机
公开(公告)号：US08707116B2
公开(公告)日：2014-04-22
申请号：US13891760
申请日：2013-05-10
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/318555 , G01R31/3177 , G01R31/318572
摘要： Operating a state machine includes enabling operation of the state machine upon receiving a signal indicating a change from operation of a test access port to a scan test port. The process maintains the state machine in an IDLE 1 state while receiving a scan test port capture signal and transitions the state machine to an IDLE 2 state when receiving a scan test port shift signal. The process then transitions the state machine to a SEQUENCE 1 state, then to a SEQUENCE 2 state, and then to a SEQUENCE 3 state when receiving sequential scan test port capture signals. The state machine then transitions to an UNLOCK TAP state and then back to the IDLE 1 state when receiving sequential scan test port shift signals on the test mode select/capture select lead.
摘要翻译：操作状态机包括在接收到指示从测试访问端口到扫描测试端口的操作的改变的信号时允许状态机的操作。当接收到扫描测试端口捕获信号时，该过程将状态机保持在空闲状态，并在接收到扫描测试端口移位信号时将状态机转变为空闲状态。然后，该过程将状态机转换为SEQUENCE 1状态，然后转换为SEQUENCE 2状态，然后在接收顺序扫描测试端口捕获信号时转换为SEQUENCE 3状态。然后，当在测试模式选择/捕获选择引线上接收顺序扫描测试端口移位信号时，状态机然后转换到解锁TAP状态，然后返回到空闲1状态。

143. 发明授权

US08700963B2 Semiconductor test system and method 有权
标题翻译：半导体测试系统及方法
公开(公告)号：US08700963B2
公开(公告)日：2014-04-15
申请号：US14074402
申请日：2013-11-07
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/26
CPC分类号： G01R31/3177 , G01R31/31703 , G01R31/318511 , G01R31/318533 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318566 , G01R31/318572 , G01R31/31926 , G01R31/31932 , G06F11/26 , G06F11/277
摘要： A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
摘要翻译：测试控制器将测试激励信号并行地施加到晶片上的多个管芯的输入焊盘。测试控制器还将编码的测试响应信号并行地应用于多个管芯的输出焊盘。编码的测试响应信号在芯片上解码，并与通过将测试激励信号应用于芯片上的核心电路产生的核心测试响应信号进行比较。该比较产生加载到IEEE 1149.1扫描路径的扫描单元中的通过/失败信号。然后可以将通过/失败信号扫描出模具以确定测试结果。

144. 发明申请

US20140101502A1 FALLING CLOCK EDGE JTAG BUS ROUTERS 审中-公开
标题翻译：时钟边缘JTAG总线路由器
公开(公告)号：US20140101502A1
公开(公告)日：2014-04-10
申请号：US14054039
申请日：2013-10-15
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/318597 , G01R31/31723 , G01R31/3177 , G01R31/318552 , G01R31/318555 , G01R31/318558
摘要： The disclosure describes a novel method and apparatus for allowing a controller to access a bus router using a communication occurring in response to one edge of a clock to select one or more devices for access using a communication occurring on the opposite edge of the clock. Additional embodiments are also provided and described in the disclosure.
摘要翻译：本公开描述了一种新颖的方法和装置，用于允许控制器使用响应于时钟的一个边缘发生的通信来访问总线路由器，以使用在时钟的相对边缘上发生的通信来选择用于访问的一个或多个设备。在本公开中还提供和描述了另外的实施例。

145. 发明授权

US08692248B2 Integrated circuit die having input and output circuit pads, test circuitry, and multiplex circuitry 有权
标题翻译：具有输入和输出电路板，测试电路和多路复用电路的集成电路管芯
公开(公告)号：US08692248B2
公开(公告)日：2014-04-08
申请号：US14068819
申请日：2013-10-31
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel , Alan Hales
IPC分类号： H01L23/58 , G01R31/26
CPC分类号： G01R31/3177 , G01R1/07342 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318566 , G01R31/318572 , G01R31/31924 , G01R31/31926
摘要： Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
摘要翻译：位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3以上）可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出芯片/ IC输出。除功能测试外，还可以对芯片和IC进行扫描测试。

146. 发明授权

US08683281B2 Scan path delay testing with two memories and three subdivisions 有权
标题翻译：扫描路径延迟测试与两个存储器和三个细分
公开(公告)号：US08683281B2
公开(公告)日：2014-03-25
申请号：US13708237
申请日：2012-12-07
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel , Joel J. Graber
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/31721 , G01R31/3177 , G01R31/318541 , G01R31/318547 , G01R31/318575 , G01R31/31858 , G01R31/318586
摘要： Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.
摘要翻译：扫描和扫描BIST架构通常用于测试集成电路中的数字电路。本公开改进了低功率扫描和扫描BIST方法。该改进允许低功耗扫描和扫描BIST架构实现与传统扫描和Scan-BIST架构中使用的延迟测试功能一样有效的延迟测试功能。

147. 发明授权

US08683279B2 Tap instruction register with four bits for TLM selection 失效
标题翻译：点击4位的指令寄存器进行TLM选择
公开(公告)号：US08683279B2
公开(公告)日：2014-03-25
申请号：US13894089
申请日：2013-05-14
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318536 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318572
摘要： A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
摘要翻译： TAP链接模块（21,51）允许通过单个TAP接口（20）从测试总线（13）控制和访问多个TAP（TAP 1-4）。

148. 发明申请

US20140082443A1 ACCELERATING SCAN TEST BY RE-USING RESPONSE DATA AS STIMULUS DATA ABSTRACT 审中-公开
标题翻译：通过将响应数据重新用作刺激数据来加速扫描测试
公开(公告)号：US20140082443A1
公开(公告)日：2014-03-20
申请号：US14085300
申请日：2013-11-20
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/318505 , G01R31/318544
摘要： Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit 2. After reset, a scan path captures the output response data from the reset stimulus from all circuits. A tester then shifts the captured data only the length of the first circuit's scan path while loading the first circuit's scan path with new test stimulus data. The new response data from all the circuits then is captured in the scan path. This shift and capture cycle is repeated until the first circuit is tested. The first circuit is then disabled and any remaining stimulus data is applied to the second circuit. This process is repeated until all the circuits are tested. A data retaining boundary scan cell used in the scan testing connects the output of an additional multiplexer as the input to a boundary cell. The inputs of the additional multiplexer connect to the data input and data output of the boundary cell.
摘要翻译：通过使用从诸如电路1的一个电路输出的扫描测试响应数据作为诸如电路2的另一电路的扫描测试激励数据，来加速诸如电路1至N的多个目标电路的扫描测试。复位时，扫描路径从所有电路的复位激励中捕获输出响应数据。然后，测试者将捕获的数据仅移动第一电路的扫描路径的长度，同时用新的测试激励数据加载第一电路的扫描路径。然后在扫描路径中捕获来自所有电路的新的响应数据。重复该移位和捕获周期直到第一个电路被测试。然后禁用第一电路，并且将任何剩余的激励数据施加到第二电路。重复该过程直到所有电路都被测试。在扫描测试中使用的数据保留边界扫描单元将附加多路复用器的输出连接到边界单元的输入。附加多路复用器的输入连接到边界单元的数据输入和数据输出。

149. 发明申请

US20140068363A1 SEMICONDUCTOR TEST SYSTEM AND METHOD 有权
标题翻译：半导体测试系统和方法
公开(公告)号：US20140068363A1
公开(公告)日：2014-03-06
申请号：US14074402
申请日：2013-11-07
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/3185
CPC分类号： G01R31/3177 , G01R31/31703 , G01R31/318511 , G01R31/318533 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318566 , G01R31/318572 , G01R31/31926 , G01R31/31932 , G06F11/26 , G06F11/277
摘要： A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
摘要翻译：测试控制器将测试激励信号并行地施加到晶片上的多个管芯的输入焊盘。测试控制器还将编码的测试响应信号并行地应用于多个管芯的输出焊盘。编码的测试响应信号在芯片上解码，并与通过将测试激励信号应用于芯片上的核心电路产生的核心测试响应信号进行比较。该比较产生加载到IEEE 1149.1扫描路径的扫描单元中的通过/失败信号。然后可以将通过/失败信号扫描出模具以确定测试结果。

150. 发明授权

US08667351B2 Input, output, and link instruction circuits for hierarchical P1500 wrappers 有权
标题翻译：用于分层P1500包装器的输入，输出和链接指令电路
公开(公告)号：US08667351B2
公开(公告)日：2014-03-04
申请号：US13892473
申请日：2013-05-13
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/31713 , G01R31/31723 , G01R31/31727 , G01R31/318508 , G01R31/318555
摘要： A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.
摘要翻译：测试架构使用链接指令寄存器（LIR）访问IC内的IP核测试包装器。正在开发IEEE P1500标准，通过称为包装器的测试结构提供对这些单独内核的测试访问。包装器位于核心的边界处，并提供了一种测试核心和核心之间互连的方法。测试架构使得IC中的多个包装器中的每一个包括嵌入在其他核心内的核心中的包装器，具有单独的使能信号。

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