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141. 发明授权

US07714357B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07714357B2
公开(公告)日：2010-05-11
申请号：US12253850
申请日：2008-10-17
申请人： Takahiro Hayashi , Shunsuke Toyoshima , Kazuo Sakamoto , Naozumi Morino , Kazuo Tanaka
发明人： Takahiro Hayashi , Shunsuke Toyoshima , Kazuo Sakamoto , Naozumi Morino , Kazuo Tanaka
IPC分类号： H01L29/74 , H01L23/52
CPC分类号： H01L23/49844 , H01L23/49811 , H01L23/50 , H01L23/5226 , H01L23/5286 , H01L23/53228 , H01L23/585 , H01L24/05 , H01L24/06 , H01L24/49 , H01L27/0255 , H01L27/092 , H01L2224/02166 , H01L2224/05025 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05624 , H01L2224/06102 , H01L2224/06133 , H01L2224/06143 , H01L2224/06153 , H01L2224/06163 , H01L2224/49105 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12036 , H01L2924/1306 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
摘要翻译：本发明的目的是提供一种能够减小半导体器件的平面尺寸的技术。在半导体衬底上形成输入/输出电路，接地布线和电源布线通过输入/输出电路，并且在其上形成用于焊盘的导电层。输入/输出电路由nMISFET形成区域和pMISFET形成区域中的MISFET元件形成，电阻元件形成区域中的电阻元件和用作保护元件的二极管元件形成区域中的二极管元件。连接到保护元件并位于接地布线和电源布线下方的布线在nMISFET形成区域和pMISFET形成区域之间以及接地布线和要连接的电源布线之间的拉出区域中拉出到导电层。

142. 发明申请

US20090202190A1 OPTICAL WAVEGUIDE 失效
标题翻译：光波导
公开(公告)号：US20090202190A1
公开(公告)日：2009-08-13
申请号：US11570410
申请日：2005-06-10
申请人： Kazuo Tanaka , Masahiro Tanaka
发明人： Kazuo Tanaka , Masahiro Tanaka
IPC分类号： G02B6/00
CPC分类号： G01Q60/22 , G02B6/262 , Y10S977/862
摘要： When light is made incident to an optical waveguide path 14 formed through a main body 12 composed of silver (Ag) that is a plasmon active medium, surface plasmon is generated on a definition face 55 of the optical waveguide path 14 (including a fine aperture 16). Thus, the intensity of the light propagating in the optical waveguide path 14 is strengthened as the light propagates toward the fine aperture 16. In addition, a distal end 51 of a first protrusive piece 13a is more protrusive as compared with a distal end 52 of a second protrusive piece 13b. Thus, in a distal end part of a projection 13, the light is focused in the vicinity of the first protrusive piece 13a based on an intensity distribution of an electric field at the distal end part. Thus, the light having seeped out from the fine aperture 16 is restricted from spreading in a polarizing direction. Therefore, the light intensity of the light propagated through the optical waveguide path 14 is increased at a low cost without causing an increase of the spread of the light while maintaining a good S/N ratio.
摘要翻译：当光入射到通过由作为等离子体激元介质的银（Ag）构成的主体12形成的光波导路径14时，在光波导路径14的定义面55（包括细孔 16）。因此，当光向微孔16传播时，在光波导路径14中传播的光的强度增强。此外，与第一突出片13a的远端52相比，第一突出片13a的远端51更突出第二突出件13b。因此，在突起13的前端部，基于前端部的电场的强度分布，将光聚焦在第一突出片13a的附近。因此，从微细孔16渗出的光被限制在偏振方向上的扩散。因此，通过光波导路径14传播的光的光强度以低成本增加，而不会导致光的扩展增加，同时保持良好的S / N比。

143. 发明申请

US20090195292A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20090195292A1
公开(公告)日：2009-08-06
申请号：US12422712
申请日：2009-04-13
申请人： Yusuke Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
发明人： Yusuke Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
IPC分类号： H03L5/00
CPC分类号： H03K19/018521 , H01L27/0928 , H01L27/105 , H03K3/356113
摘要： A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.
摘要翻译：提供了包括能够以低成本进行低电压高速运行的I / O电路的半导体集成电路装置。在I / O电路中，当I / O电压（例如3.3V）降低到预定电压（例如1.8V）时，导致速度劣化的部分是电平转换单元和预缓冲单元用于驱动主要大型缓冲区。鉴于此，高电压被施加到电平转换器和预缓冲器电路。通过这样做，可以以低成本实现能够进行低电压高速操作的I / O电路。

144. 发明申请

US20090159646A1 CONDUCTIVE BALL REMOVING METHOD, CONDUCTIVE BALL MOUNTING METHOD, CONDUCTIVE BALL REMOVING APPARATUS, AND CONDUCTIVE BALL MOUNTING APPARATUS 有权
标题翻译：导电球去除方法，导电球安装方法，导电球去除装置和导电球安装装置
公开(公告)号：US20090159646A1
公开(公告)日：2009-06-25
申请号：US12336875
申请日：2008-12-17
申请人： Kazuo Tanaka , Kiyoaki Iida , Hideaki Sakaguchi , Nobuyuki Machida
发明人： Kazuo Tanaka , Kiyoaki Iida , Hideaki Sakaguchi , Nobuyuki Machida
IPC分类号： B23K1/20 , B23K3/06
CPC分类号： B23K3/0623 , H01L24/11 , H01L24/742 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/11005 , H01L2224/11334 , H01L2224/13005 , H01L2224/13147 , H01L2224/1319 , H01L2224/13561 , H01L2224/1357 , H01L2224/136 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H05K3/3478 , H05K2203/0191 , H05K2203/041 , H05K2203/0557 , H01L2924/20751 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： In a method of removing conductive balls that are left on a mask provided on a substrate having pads thereon, the method includes: (a) making a sheet member close to the mask using a contacting mechanism such that a gap between the sheet member and the mask is set small than a diameter of the conductive balls. The conductive balls are removed in such a manner that the conductive balls are adhered onto the sheet member.
摘要翻译：在除去设置在其上具有衬垫的衬底上的掩模上的导电球的方法中，该方法包括：（a）使用接触机构使片状构件靠近掩模，使得片构件和掩模被设定为小于导电球的直径。以这样的方式去除导电球，使得导电球粘附到片状构件上。

145. 发明申请

US20090054646A1 Method for Production of Quinazolin 4-One Derivative 失效
标题翻译： Quinazolin 4-One衍生物的生产方法
公开(公告)号：US20090054646A1
公开(公告)日：2009-02-26
申请号：US12282381
申请日：2007-03-14
申请人： Kazuo Tanaka , Yoshifumi Sato , Takafumi Yoshimura
发明人： Kazuo Tanaka , Yoshifumi Sato , Takafumi Yoshimura
IPC分类号： C07D239/88
CPC分类号： C07D239/88
摘要： In reacting an anthranilic acid derivative represented by the general formula (1), especially the anthranilic acid derivative selected from anthranilic acid, anthranilamide and anthranilate, with formamide, the reaction is attained under the condition of coexistence of acetic acid and a base as a catalyst in the reaction liquid, and it has made it possible to produce a quinazolin-4-one derivative represented by the general formula (2) and useful as a material for medicine intermediates, at high yield with no side production.
摘要翻译：在使通式（1）表示的邻氨基苯甲酸衍生物，特别是选自邻氨基苯甲酸，邻氨基苯甲酰胺和邻氨基苯甲酸酯的邻氨基苯甲酸衍生物与甲酰胺反应时，在乙酸和碱作为催化剂共存的条件下反应在反应液中，可以以高产率生产无副产物的由通式（2）表示的喹唑啉-4-酮衍生物作为医药中间体的材料。

146. 发明授权

US07425845B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07425845B2
公开(公告)日：2008-09-16
申请号：US11452238
申请日：2006-06-14
申请人： Takeo Toba , Kazuo Tanaka , Shunsuke Toyoshima
发明人： Takeo Toba , Kazuo Tanaka , Shunsuke Toyoshima
IPC分类号： H03K19/0185
CPC分类号： G11C5/147 , G11C7/1066 , G11C11/4074
摘要： The present invention provides a semiconductor integrated circuit having two kinds of input/output circuits realizing higher speed and higher packing density with rational configuration. The semiconductor integrated circuit has a first input/output circuit operating on a first power source voltage, an internal circuit operating on a second power source voltage lower than the first power source voltage, and a second input/output circuit operating on a third power source voltage lower than the first power source voltage. In an output circuit of the first input/output circuit, signal amplitude corresponding to the second power source voltage is converted to signal amplitude corresponding to the first power source voltage by a level shifter, and a P-channel MOSFET and an N-channel MOSFET constructing the output circuit are driven. In an output circuit of the second input/output circuit, a drive signal is generated by a level shifter in a manner similar to the above to drive second and third N-channel MOSFETs for generating an output signal having signal amplitude corresponding to the third power source voltage.
摘要翻译：本发明提供一种具有两种输入/输出电路的半导体集成电路，其实现了具有合理配置的更高速度和更高的封装密度。半导体集成电路具有以第一电源电压工作的第一输入/输出电路，以及低于第一电源电压的第二电源电压运行的内部电路，以及在第三电源上运行的第二输入/输出电路电压低于第一电源电压。在第一输入/输出电路的输出电路中，对应于第二电源电压的信号幅度由电平移位器转换成对应于第一电源电压的信号幅度，以及P沟道MOSFET和N沟道MOSFET 驱动输出电路的构造。在第二输入/输出电路的输出电路中，以与上述类似的方式由电平转换器产生驱动信号，以驱动第二和第三N沟道MOSFET，以产生具有对应于第三功率的信号幅度的输出信号源电压。

147. 发明申请

US20080173899A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080173899A1
公开(公告)日：2008-07-24
申请号：US11970512
申请日：2008-01-07
申请人： Koichiro TAKAKUWA , Kazuo Tanaka
发明人： Koichiro TAKAKUWA , Kazuo Tanaka
IPC分类号： H01L27/10
CPC分类号： H01L27/0251 , H01L23/5286 , H01L24/06 , H01L2924/1306 , H01L2924/13091 , H01L2924/3011 , H01L2924/00
摘要： There is provided a technology which allows sufficient protection of internal circuits from electrostatic discharge even when internal-circuit power source pads and internal-circuit GND pads are formed on an internal circuit region. Internal-circuit power source pads and internal-circuit GND pads are placed in the core region of a semiconductor chip. Between the internal-circuit power source pads and the internal-circuit GND pads, the internal circuits are formed. Between the internal-circuit power source pads and the internal-circuit GND pads, electrostatic protection circuits for protecting the internal circuits from a surge current are further formed. Each of the electrostatic protection circuits is composed of a discharge circuit for causing the surge current to flow therein and a control circuit for controlling the discharge circuit. The present invention is characterized in that the discharge circuits are placed in the core region and the control circuits are placed in an I/O region.
摘要翻译：即使在内部电路区域上形成内部电路电源焊盘和内部电路GND焊盘的情况下，也提供了能够充分保护内部电路免受静电放电的技术。内部电路电源焊盘和内部电路GND焊盘放置在半导体芯片的芯区域中。内部电源焊盘与内部电路GND焊盘之间形成内部电路。在内部电源焊盘和内部电路GND焊盘之间，进一步形成用于保护内部电路免受浪涌电流的静电保护电路。每个静电保护电路由用于使浪涌电流流过的放电电路和用于控制放电电路的控制电路组成。本发明的特征在于，将放电电路放置在芯区域中，将控制电路放置在I / O区域中。

148. 发明授权

US07346273B2 Substrate processing equipment 有权
标题翻译：基板加工设备
公开(公告)号：US07346273B2
公开(公告)日：2008-03-18
申请号：US10550202
申请日：2004-06-18
申请人： Kazuo Tanaka , Masaaki Ueno , Masashi Sugishita
发明人： Kazuo Tanaka , Masaaki Ueno , Masashi Sugishita
IPC分类号： F26B3/30 , H05B3/02
CPC分类号： H01L21/67248 , G05D23/1928 , G05D23/22 , H01L21/67109
摘要： It is an object of the invention to provide a substrate processing equipment that can predict a temperature of a substrate and easily control temperature of the substrate. Formed in a reactor (processing chamber) 3 are four temperature adjustment zones, of which setting and adjustment of temperature can be made by zone heaters 340-1 to 340-4. A temperature controller 4 mixes temperatures detected by inner thermocouples 302-1 to 302-4 and outer thermocouples 342-1 to 342-4 to calculate predicted temperatures of substrates by means of the first-order lag calculation on the basis of time constants of temperatures of substrates heated by the zone heaters 340-1 to 340-4. Also, the temperature controller 4 calculates electric power values (operating variables) for the zone heaters 340-1 to 340-4 with the use of predicted temperatures of substrates to output the same to the zone heaters 340-1 to 340-4.
摘要翻译：本发明的目的是提供一种能够预测基板的温度并容易地控制基板的温度的基板处理设备。在反应器（处理室）3中形成的是四个温度调节区域，其中温度的设定和调节可以由区域加热器340-1至340-4进行。温度控制器4将由内部热电偶302-1至302-4检测的温度与外部热电偶342-1至342-4混合，以基于温度的时间常数通过一阶滞后计算来计算衬底的预测温度的区域加热器340-1至340-4加热的基底。此外，温度控制器4使用基板的预测温度来计算区域加热器340-1至340-4的电功率值（操作变量），以将其输出到区域加热器340-1至340-4。

149. 外观设计

USD556264S1 Advertising pillar 有权
公开(公告)号：USD556264S1
公开(公告)日：2007-11-27
申请号：US29269832
申请日：2006-12-11
申请人： Kazuo Tanaka , Toshihiko Irie , Haruo Nozaki
设计人： Kazuo Tanaka , Toshihiko Irie , Haruo Nozaki

150. 发明授权

US07205396B2 Benzodeazaadenine derivative base and electronic material containing the same 失效
标题翻译：苯并恶唑衍生物基质和含有它们的电子材料
公开(公告)号：US07205396B2
公开(公告)日：2007-04-17
申请号：US10508138
申请日：2002-08-15
申请人： Isao Saito , Akimitsu Okamoto , Kazuo Tanaka
发明人： Isao Saito , Akimitsu Okamoto , Kazuo Tanaka
IPC分类号： C07H21/00 , C07H21/02 , C12Q1/68
CPC分类号： C07H21/04 , B82Y10/00 , C07H19/04 , C07H19/22 , C07H19/23 , H01L51/0072 , H01L51/0093
摘要： A nucleic acid base for hole transportation in DNAs which does not cause oxidative decomposition; and an artificial DNA molecule which can realize effective hole transportation in DNAs while maintaining the double spiral structure of the DNAs. Provided are: a nucleic acid which contains a benzodeazaadenine derivative base represented by the general formula (I): (wherein R1, R2, R3, R4, R5, and R6 each independently represents hydrogen, amino, mono (lower alkyl) amino, di (lower alkyl) amino, hydroxy, lower alkoxy, halogeno, cyano, mercapto, lower alkylthio, or aryl; and R7 and R8 each independently represents hydrogen or a group bonded to phosphoric acid); and a polynucleotide comprising the nucleic acid.
摘要翻译： DNA不会引起氧化分解的空穴传输核酸碱基; 以及能够在保持DNA的双螺旋结构的同时实现DNA中有效空穴传输的人造DNA分子。提供：含有由通式（I）表示的苯并恶唑烷衍生物碱的核酸：

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