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141. 发明申请

US20130062699A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130062699A1
公开(公告)日：2013-03-14
申请号：US13576550
申请日：2011-11-25
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/04 , H01L21/336
CPC分类号： H01L29/785 , H01L27/0924 , H01L29/66795
摘要： A semiconductor device and a method for manufacturing the same are disclosed. In one embodiment, the semiconductor device may comprise a semiconductor layer, a fin formed by patterning the semiconductor layer, and a gate stack crossing over the fin. The fin may comprise a doped block region at the bottom portion thereof. According to the embodiment, it is possible to effectively suppress current leakage at the bottom portion of the fin by the block region.
摘要翻译：公开了一种半导体器件及其制造方法。在一个实施例中，半导体器件可以包括半导体层，通过图案化半导体层形成的鳍和跨在翅片上的栅极堆叠。鳍可以在其底部包括掺杂块区域。根据本实施方式，能够通过块区域有效地抑制翅片底部的电流泄漏。

142. 发明申请

US20130056829A1 Semiconductor Structure and Method for Manufacturing the Same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130056829A1
公开(公告)日：2013-03-07
申请号：US13504935
申请日：2011-11-30
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/092 , H01L21/02
CPC分类号： H01L27/124 , H01L21/743 , H01L27/1218 , H01L29/78
摘要： The present invention relates to a semiconductor structure and a method for manufacturing the same. A semiconductor structure comprises: a semiconductor substrate; a first insulating material layer, a first conductive material layer, a second insulating material layer, a second conductive material layer and an insulating buried layer formed in sequence on the semiconductor substrate; a semiconductor layer bonded on the insulating buried layer; transistors formed on the semiconductor layer, the channel regions of the transistors each being formed in the semiconductor layer and each having a back-gate formed from the second conductive material layer; a dielectric layer covering the semiconductor layer and the transistors; isolation structures for at least electrically isolating each transistor from its adjacent transistors, the top of the isolation structures being flush with or slightly higher than the upper surface of the semiconductor layer, and the bottom of the isolation structures being in the second insulating material layer; and a conductive contact running through the dielectric layer and extending down into the first conductive material layer.
摘要翻译：半导体结构及其制造方法技术领域本发明涉及半导体结构及其制造方法。半导体结构包括：半导体衬底; 在半导体衬底上依次形成第一绝缘材料层，第一导电材料层，第二绝缘材料层，第二导电材料层和绝缘掩埋层; 接合在绝缘掩埋层上的半导体层; 形成在半导体层上的晶体管，晶体管的沟道区各自形成在半导体层中，每一个具有由第二导电材料层形成的背栅; 覆盖半导体层和晶体管的电介质层; 用于至少将每个晶体管与其相邻晶体管电隔离的隔离结构，隔离结构的顶部与半导体层的上表面齐平或略高，隔离结构的底部位于第二绝缘材料层中; 以及导电接触件，其穿过介电层并向下延伸到第一导电材料层中。

143. 发明授权

US08377777B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08377777B2
公开(公告)日：2013-02-19
申请号：US12999796
申请日：2010-09-17
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L27/088 , H01L21/8232
CPC分类号： H01L21/823468 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： A semiconductor device includes a semiconductor substrate; gates, spacers on both sides of the respective gates, and source and gain regions on both sides of the respective spacers, which are formed on the semiconductor substrate; lower contacts located on the respective source and gain regions and abutting outer-sidewalls of the spacers, with bottoms covering at least a portion of the respective source and gain regions; an inter-layer dielectric layer formed on the gates, the spacers, the source and gain regions, and the lower contacts, wherein the respective source and gain regions of each of the transistor structures are isolated from each other by the inter-layer dielectric layer; and upper contacts formed in the inter-layer dielectric layer and corresponding to the lower contacts. Methods for fabricating such a semiconductor device and for manufacturing contacts for semiconductor devices.
摘要翻译：半导体器件包括半导体衬底; 各个栅极的两侧的栅极，间隔物，以及形成在半导体衬底上的各个间隔物的两侧的源极和增益区域; 下部触点位于相应的源极和增益区域以及邻接的间隔物的外侧壁上，底部覆盖相应的源极和增益区域的至少一部分; 形成在栅极，间隔物，源极和增益区域以及下部触点上的层间电介质层，其中每个晶体管结构的各个源极和增益区域通过层间电介质层彼此隔离 ; 以及形成在层间电介质层中并对应于下触点的上触点。用于制造这种半导体器件和用于制造用于半导体器件的触点的方法。

144. 发明申请

US20120280305A1 FLASH MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：闪存存储器件及其制造方法
公开(公告)号：US20120280305A1
公开(公告)日：2012-11-08
申请号：US13062024
申请日：2010-09-26
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/823456 , H01L21/82385 , H01L27/112 , H01L27/11206 , H01L27/11519 , H01L27/11541 , H01L27/11543 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： The present invention discloses a flash memory device. The flash memory device comprises a semiconductor substrate and a flash memory area located on the semiconductor substrate. The flash memory area comprises a first doped well, which is divided into a first region and a second region by an isolation region, the second region being doped with an impurity having an electrical conductivity opposite to that of the first doped well; a high-k gate dielectric layer located on the first doped well; and a metal layer located on the high-k gate dielectric layer. The present invention enables compatibility between the high-k dielectric metal gate and the erasable flash memory and increases the operation performance of the flash memory. The present invention also provides a manufacturing method of the flash memory device, which greatly increases the production efficiency and yield of flash memory devices.
摘要翻译：本发明公开了一种闪存装置。闪存器件包括半导体衬底和位于半导体衬底上的闪存区域。闪存区域包括第一掺杂阱，其通过隔离区域分成第一区域和第二区域，第二区域掺杂有与第一掺杂阱的导电性相反的导电性的杂质; 位于第一掺杂阱上的高k栅介质层; 以及位于高k栅介质层上的金属层。本发明实现了高k电介质金属栅极和可擦除闪存之间的兼容性，并且提高了闪速存储器的操作性能。本发明还提供一种快闪存储器件的制造方法，其大大提高了闪速存储器件的生产效率和产量。

145. 发明申请

US20120273840A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120273840A1
公开(公告)日：2012-11-01
申请号：US13379533
申请日：2011-04-25
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L29/267 , H01L21/76
CPC分类号： H01L21/02647 , H01L21/02639 , H01L21/76229
摘要： A semiconductor structure and a method for manufacturing the same are disclosed. The method comprises: disposing a first dielectric material layer on a first semiconductor layer and defining openings in the first dielectric material layer; epitaxially growing a second semiconductor layer on the first semiconductor layer via the openings defined in the first dielectric material layer, wherein the second semiconductor layer and the first semiconductor layer comprise different materials from each other; and forming plugs of a second dielectric material in the second semiconductor layer at positions where the openings are defined in the first dielectric material layer and also at middle positions between adjacent openings. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed.
摘要翻译：公开了一种半导体结构及其制造方法。该方法包括：在第一半导体层上设置第一介电材料层并在第一介电材料层中限定开口; 通过限定在第一介电材料层中的开口在第一半导体层上外延生长第二半导体层，其中第二半导体层和第一半导体层包括彼此不同的材料; 以及在所述第二半导体层中形成所述第一介电材料层中所述开口的位置以及在相邻开口之间的中间位置处形成第二电介质材料的插塞。根据本公开的实施例，可以有效地抑制在异质外延生长期间发生的缺陷。

146. 发明申请

US20120181623A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120181623A1
公开(公告)日：2012-07-19
申请号：US13380362
申请日：2011-02-27
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823437 , H01L21/823418 , H01L29/49 , H01L29/66545 , H01L29/7833
摘要： It is provided a method for forming a semiconductor device comprising: forming a material layer which exposes dummy gates and sidewall spacers and fills spaces between two adjacent gate stacks, and the material of the material layer is the same as the material of the dummy gate; removing the dummy gates and the material layer to form recesses; filling the recesses with a conductive material, and planarizing the conductive material to expose the sidewall spacers; breaking the conductive material outside the sidewall spacers to form at least two conductors, each of the conductors being only in contact with the active region at one side outside one of the sidewall spacers, so as to form gate stack structures and first contacts. Besides, a semiconductor device is provided. The method and the semiconductor device are favorable for extending process windows in forming contacts.
摘要翻译：提供一种用于形成半导体器件的方法，包括：形成暴露伪栅极和侧壁间隔物并填充两个相邻栅极堆叠之间的空间的材料层，并且材料层的材料与虚拟栅极的材料相同; 去除虚拟门和材料层以形成凹槽; 用导电材料填充凹部，并平坦化导电材料以暴露侧壁间隔物; 将导电材料破坏在侧壁间隔物外部以形成至少两个导体，每个导体仅在侧壁间隔件之外的一侧处与有源区域接触，以便形成栅叠层结构和第一触点。此外，提供了半导体器件。该方法和半导体器件有利于在形成触点时延长工艺窗口。

147. 发明申请

US20120132990A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120132990A1
公开(公告)日：2012-05-31
申请号：US13138053
申请日：2011-03-04
申请人： Huilong Zhu , Qiangqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qiangqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/78648 , H01L29/42384 , H01L29/66772 , H01L29/78603
摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. A semiconductor structure according to the present invention can adjust the threshold voltage by capacitive coupling between a backgate region either and a source region or a drain region with a common contact, i.e. a source contact or a drain contact, which leads to a simple manufacturing process, a higher integration level, and a lower manufacture cost. Moreover, the asymmetric design of the backgate structure, together with the doping of the backgate region which can be varied as required in an actual device design, can further enhance the effects of adjusting the threshold voltage and improve the performances of the device.
摘要翻译：本申请公开了一种半导体结构及其制造方法。根据本发明的半导体结构可以通过在具有公共接触的源极区域或漏极区域之间的电容耦合来调节阈值电压，即源极接触或漏极接触，这导致简单的制造过程，更高的集成度，更低的制造成本。此外，背栅结构的非对称设计以及可以根据实际器件设计中所需而改变的背栅区域的掺杂，可以进一步增强调节阈值电压并提高器件性能的效果。

148. 发明申请

US20120112249A1 HIGH PERFORMANCE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：高性能半导体器件及其制造方法
公开(公告)号：US20120112249A1
公开(公告)日：2012-05-10
申请号：US12995030
申请日：2010-06-25
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/105 , H01L29/66537 , H01L29/66545
摘要： A method for fabricating a semiconductor device employs the way of first performing thermal annealing to the source/drain regions and then forming an ion-implanted region, such as a retrograde well. The method comprises the steps of: removing said dummy gate so as to expose said dummy gate dielectric layer and form an opening; performing ion implantation on the substrate from the opening to form an ion-implanted region; removing the dummy gate dielectric layer; performing thermal annealing to activate the dopants of the ion-implanted region; and depositing a new gate dielectric layer and a new metal gate in the opening in sequence, wherein the formed new gate dielectric layer covers the substrate and the inner walls of the sidewall spacers. By means of the present invention, it is possible to avoid inappropriately introducing the dopants of the ion-implanted region into the source region and the drain region, such that the profile of the ion-implanted region does not overlap with the dopants of the source/drain regions, thereby avoiding increasing the band-to-band leakage current in a MOSFET device. As a result, the performance of the device is improved.
摘要翻译：用于制造半导体器件的方法采用首先对源极/漏极区进行热退火，然后形成离子注入区域（例如逆行阱）的方式。该方法包括以下步骤：去除所述虚拟栅极以暴露所述伪栅介质层并形成开口; 从开口对衬底进行离子注入以形成离子注入区域; 去除所述伪栅介质层; 进行热退火以激活离子注入区域的掺杂剂; 并且依次在开口中沉积新的栅极介电层和新的金属栅极，其中所形成的新的栅极介电层覆盖基板和侧壁间隔物的内壁。通过本发明，可以避免不适当地将离子注入区域的掺杂剂引入源极区域和漏极区域，使得离子注入区域的轮廓与源极的掺杂剂不重叠 /漏极区域，从而避免增加MOSFET器件中的带间漏电流。结果，改善了设备的性能。

149. 发明申请

US20120108032A1 METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH STRESSED TRENCH ISOLATION 有权
标题翻译：用于形成具有应力分离分离的半导体器件的方法
公开(公告)号：US20120108032A1
公开(公告)日：2012-05-03
申请号：US13201371
申请日：2011-01-27
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L21/76
CPC分类号： H01L29/045 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/7846
摘要： A method for forming a semiconductor device with stressed trench isolation is provided, comprising: providing a silicon substrate (S11); forming at least two first trenches in parallel on the silicon substrate and forming a first dielectric layer which is under tensile stress in the first trenches (S12); forming at least two second trenches, which have an extension direction perpendicular to that of the first trenches, in parallel on the silicon substrate, and forming a second dielectric layer in the second trenches (S13); and after forming the first trenches, forming a gate stack on a part of the silicon substrate between two adjacent first trenches, wherein the channel length direction under the gate stack is parallel to the extension direction of the first trenches (S14). The present invention supply tensile stress in the channel width direction of a MOS transistor, so as to improve performance of PMOS and/or NMOS transistors.
摘要翻译：提供一种用于形成具有应力沟槽隔离的半导体器件的方法，包括：提供硅衬底（S11）; 在所述硅衬底上平行地形成至少两个第一沟槽，并形成在所述第一沟槽中处于拉伸应力的第一介电层（S12）; 在所述硅衬底上形成平行于所述硅衬底的至少两个具有与所述第一沟槽的延伸方向垂直的第二沟槽，以及在所述第二沟槽中形成第二电介质层（S13）。并且在形成第一沟槽之后，在两个相邻的第一沟槽之间的硅衬底的一部分上形成栅极叠层，其中栅叠层下方的沟道长度方向平行于第一沟槽的延伸方向（S14）。本发明在MOS晶体管的沟道宽度方向上提供拉伸应力，以提高PMOS和/或NMOS晶体管的性能。

150. 发明申请

US20120056267A1 HYBRID CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：混合通道半导体器件及其形成方法
公开(公告)号：US20120056267A1
公开(公告)日：2012-03-08
申请号：US13142790
申请日：2011-04-11
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/8258
摘要： A hybrid channel semiconductor device and a method for forming the same are provided. The method includes: providing a first semiconductor layer, the first semiconductor layer including an NMOS area and a PMOS area, a surface of the first semiconductor layer being covered by a second semiconductor layer, wherein electrons have higher mobility than holes in one of the first semiconductor layer and the second semiconductor layer, and holes have higher mobility than electrons in the other; forming a first dummy gate structure, and a first source region and a first drain region on respective sides of the first dummy gate structure on the second semiconductor layer in the NMOS area, forming a second dummy gate structure, and a second source region and a second drain region on respective sides of the second dummy gate structure on the second semiconductor layer in the PMOS area; forming an interlayer dielectric layer on the second semiconductor layer and performing planarization; removing the first dummy gate structure and the second dummy gate structure to form a first opening and a second opening; and forming a first gate structure on the one of the first semiconductor layer and the second semiconductor layer in which electrons have higher mobility in the first opening, and forming a second gate structure on the other semiconductor layer in the second opening. The invention can reduce defects in the channel region.
摘要翻译：提供混合通道半导体器件及其形成方法。该方法包括：提供第一半导体层，第一半导体层包括NMOS区域和PMOS区域，第一半导体层的表面被第二半导体层覆盖，其中电子具有比第一半导体层半导体层和第二半导体层，并且空穴在另一个中具有比电子更高的迁移率; 在所述NMOS区域中的所述第二半导体层上形成第一虚拟栅极结构以及所述第一虚拟栅极结构的相应侧上的第一源极区域和第一漏极区域，形成第二虚拟栅极结构，以及第二源极区域和在PMOS区域中的第二半导体层上的第二虚设栅极结构的相应侧上的第二漏极区域; 在所述第二半导体层上形成层间电介质层并进行平坦化; 去除第一虚拟栅极结构和第二虚拟栅极结构以形成第一开口和第二开口; 以及在所述第一半导体层和所述第二半导体层中的所述第一开口中形成具有较高迁移率的第一栅极结构，以及在所述第二开口中的另一半导体层上形成第二栅极结构。本发明可以减少通道区域的缺陷。

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