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141. 发明授权

US08119474B2 High performance capacitors in planar back gates CMOS 有权
标题翻译：平面后门CMOS中的高性能电容器
公开(公告)号：US08119474B2
公开(公告)日：2012-02-21
申请号：US12688243
申请日：2010-01-15
申请人： Andres Bryant , Edward J. Nowak , Richard Q. Williams
发明人： Andres Bryant , Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0811 , H01L28/40 , H01L29/78648 , Y10T436/235 , Y10T436/25125 , Y10T436/2525 , Y10T436/25375
摘要： A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.
摘要翻译：一种双栅极CMOS结构的制造方法和器件。该结构包括绝缘层中的第一板和与第一板电对应的绝缘层之上的第二板。隔离结构在第一板和第二板之间。

142. 发明申请

US20110101449A1 ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 有权
标题翻译：不对称场效应晶体管结构与方法
公开(公告)号：US20110101449A1
公开(公告)日：2011-05-05
申请号：US12985060
申请日：2011-01-05
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).
摘要翻译：公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供改进的驱动电流，电路延迟最小）。具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定的电容值）。

143. 发明申请

US20110068399A1 INTEGRATED CIRCUIT DEVICE WITH SERIES-CONNECTED FIELD EFFECT TRANSISTORS AND INTEGRATED VOLTAGE EQUALIZATION AND METHOD OF FORMING THE DEVICE 有权
标题翻译：具有串联场效应晶体管和集成电压均衡的集成电路装置及其形成方法
公开(公告)号：US20110068399A1
公开(公告)日：2011-03-24
申请号：US12563195
申请日：2009-09-21
申请人： Andres Bryant , Edward J. Nowak
发明人： Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/786 , H01L29/78 , H01L21/336
CPC分类号： H01L21/845 , H01L21/84 , H01L27/1203 , H01L27/1211
摘要： Disclosed is an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device. The series-connected FETs comprise gates positioned along a semiconductor body to define the channel regions for the series-connected FETs. Source/drain regions are located within the semiconductor body on opposing sides of the channel regions such that each portion of the semiconductor body between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor. Integrated voltage equalization is achieved through a conformal conductive layer having a desired resistance and positioned over the series-connected FETs such that it is electrically isolated from the gates, but in contact with the source/drain regions within the semiconductor body.
摘要翻译：公开了具有集成电压均衡的具有串联的平面或非平面场效应晶体管（FET）的集成电路器件和形成器件的方法。串联连接的FET包括沿着半导体本体定位的门，以限定用于串联连接的FET的沟道区。源极/漏极区域位于沟道区域的相对侧上的半导体本体内，使得相邻栅极之间的半导体本体的每个部分包括用于一个场效应晶体管的一个源极/漏极区域，用于与另一个场效应晶体管的另一个源极/漏极区域相邻接。集成电压均衡通过具有期望电阻的并行导电层实现，并且位于串联连接的FET上，使得其与栅极电隔离，但与半导体本体内的源极/漏极区域接触。

144. 发明授权

US07902000B2 MugFET with stub source and drain regions 有权
标题翻译： MugFET具有短路源极和漏极区域
公开(公告)号：US07902000B2
公开(公告)日：2011-03-08
申请号：US12132865
申请日：2008-06-04
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/72
CPC分类号： H01L29/785 , H01L29/66803
摘要： The present invention provides a semiconductor device that includes at least one semiconductor Fin structure atop the surface of a substrate; the semiconducting fin structure including a channel of a first conductivity type and source/drain regions of a second conductivity type, the source/drain regions present at each end of the semiconductor fin structure; a gate structure immediately adjacent to the semiconductor fin structure, a dielectric spacer abutting each sidewall of the gate structure wherein the each end of the fin structure extends a dimension that is less than about ¼ a length of the Si-containing fin structure from a sidewall of the dielectric spacer; and a semiconductor region to the each end of the semiconductor fin structure, wherein the semiconductor region to the each end of the semiconductor fin structure is separated from the gate structure by the dielectric spacer.
摘要翻译：本发明提供一种半导体器件，其包括在衬底的表面上方的至少一个半导体鳍结构; 所述半导体鳍结构包括第一导电类型的沟道和第二导电类型的源极/漏极区，所述源/漏区存在于所述半导体鳍结构的每个端部处; 靠近半导体鳍片结构的栅极结构，邻接栅极结构的每个侧壁的电介质间隔物，其中翅片结构的每个端部从侧壁延伸小于约含有Si的鳍结构的长度的尺寸的电介质间隔物; 以及到半导体鳍片结构的每一端的半导体区域，其中半导体鳍片结构的每个端部的半导体区域通过电介质间隔物与栅极结构分离。

145. 发明授权

US07847320B2 Dense chevron non-planar field effect transistors and method 有权
标题翻译：密集V形非平面场效应晶体管及方法
公开(公告)号：US07847320B2
公开(公告)日：2010-12-07
申请号：US11939574
申请日：2007-11-14
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/80
CPC分类号： H01L27/0207 , H01L21/823412 , H01L29/785
摘要： Disclosed are embodiments of semiconductor structure and a method of forming the semiconductor structure that simultaneously maximizes device density and avoids contacted-gate pitch and fin pitch mismatch, when multiple parallel angled fins are formed within a limited area on a substrate and then traversed by multiple parallel gates (e.g., in the case of stacked, chevron-configured, CMOS devices). This is accomplished by using, not a minimum lithographic fin pitch, but rather by using a fin pitch that is calculated as a function of a pre-selected contacted-gate pitch, a pre-selected fin angle and a pre-selected periodic pattern for positioning the fins relative to the gates within the limited area. Thus, the disclosed structure and method allow for the conversion of a semiconductor product design layout with multiple, stacked, planar FETs in a given area into a semiconductor product design layout with multiple, stacked, chevron-configured, non-planar FETs in the same area.
摘要翻译：公开了半导体结构的实施例以及形成半导体结构的方法，其同时使器件密度最大化并避免接触栅极间距和鳍片间距失配，当在衬底上的有限区域内形成多个平行的有角度的鳍片然后穿过多个平行门（例如，在堆叠，人字形配置的CMOS设备的情况下）。这是通过使用而不是最小光刻鳍间距来实现的，而是通过使用根据预先选择的接触栅间距，预选翅片角和预选择的周期性图案计算的鳍间距来实现在有限的区域内相对于门定位翅片。因此，所公开的结构和方法允许将具有给定区域中的多个堆叠的平面FET的半导体产品设计布局转换成具有多个，堆叠的，人造V形的非平面FET的半导体产品设计布局区。

146. 发明申请

US20100301419A1 INTEGRATED CIRCUIT DEVICE WITH DEEP TRENCH ISOLATION REGIONS FOR ALL INTER-WELL AND INTRA-WELL ISOLATION AND WITH A SHARED CONTACT TO A JUNCTION BETWEEN ADJACENT DEVICE DIFFUSION REGIONS ANDAN UNDERLYING FLOATING WELL SECTION 有权
标题翻译：集成电路设备，具有深层隔离隔离区域，用于所有内部和内部隔离以及与共享设备扩展区域之间的连接的共享接触，并且基于浮动井段
公开(公告)号：US20100301419A1
公开(公告)日：2010-12-02
申请号：US12473324
申请日：2009-05-28
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L27/088 , H01L29/772 , H01L21/335 , H01L21/8234
CPC分类号： H01L27/0207 , H01L21/823481 , H01L21/823493 , H01L27/092 , H01L27/11 , H01L27/1104
摘要： Disclosed are embodiments of an improved integrated circuit device structure (e.g., a static random access memory array structure or other integrated circuit device structure incorporating both P-type and N-type devices) and a method of forming the structure that uses DTI regions for all inter-well and intra-well isolation and, thereby provides a low-cost isolation scheme that avoids FET width variations due to STI-DTI misalignment. Furthermore, because the DTI regions used for intra-well isolation effectively create some floating well sections, which must each be connected to a supply voltage (e.g., Vdd) to prevent threshold voltage (Vt) variations, the disclosed integrated circuit device also includes a shared contact to a junction between the diffusion regions of adjacent devices and an underlying floating well section. This shared contact eliminates the cost and area penalties that would be incurred if a discrete supply voltage contact was required for each floating well section.
摘要翻译：公开了改进的集成电路器件结构（例如，并入P型和N型器件的静态随机存取存储器阵列结构或其他集成电路器件结构）的实施例，以及形成使用DTI区域的结构的方法从而提供了一种低成本的隔离方案，可避免由于STI-DTI失准导致的FET宽度变化。此外，由于用于井内隔离的DTI区域有效地创建了一些浮动阱区段，其必须各自连接到电源电压（例如Vdd）以防止阈值电压（Vt）变化，所公开的集成电路器件还包括与相邻设备的扩散区域和下面的浮动井段之间的连接处共享接触。这种共享联系消除了如果每个浮动井段需要离散的电源电压接触将导致的成本和面积罚款。

147. 发明授权

US07759179B2 Multi-gated, high-mobility, density improved devices 失效
标题翻译：多门控，高移动性，密度改善设备
公开(公告)号：US07759179B2
公开(公告)日：2010-07-20
申请号：US12023347
申请日：2008-01-31
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/26513 , H01L21/26546 , H01L21/26586 , H01L21/845 , H01L29/66803 , H01L29/785
摘要： Disclosed herein are embodiments of an improved method of forming p-type and n-type MUGFETs with high mobility crystalline planes in high-density, chevron-patterned, CMOS devices. Specifically, semiconductor fins are formed in a chevron layout oriented along the centerline of a wafer. Gates are formed adjacent to the semiconductor fins such that they are approximately perpendicular to the centerline. Then, masked implant sequences are performed, during which halo and/or source/drain dopants are implanted into the sidewalls of the semiconductor fins on one side of the chevron layout and then into the sidewalls of the semiconductor fins on the opposite side of the chevron layout. The implant direction used during these implant sequences is substantially orthogonal to the gates in order to avoid mask shadowing, which can obstruct dopant implantation when separation between the semiconductor fins in the chevron layout is scaled (i.e., when device density is increased).
摘要翻译：本文公开了在高密度，人字纹图案化的CMOS器件中形成具有高迁移率晶面的p型和n型MUGFET的改进方法的实施方案。具体地，半导体散热片形成为沿着晶片的中心线定向的人字形布局。门形成在半导体翅片附近，使得它们大致垂直于中心线。然后，进行掩蔽的植入序列，在此期间将卤素和/或源极/漏极掺杂剂注入到人字形布局的一侧上的半导体鳍片的侧壁中，然后进入人字纹相反侧的半导体鳍片的侧壁布局。在这些植入序列期间使用的植入方向基本上与栅极正交，以避免掩模阴影，当阴影布局中的半导体鳍片之间的间隔被缩放时（即，当器件密度增加时），这可能阻碍掺杂剂注入。

148. 发明授权

US07745879B2 Method of fabricating high voltage fully depleted SOI transistor and structure thereof 失效
标题翻译：制造高电压全耗尽SOI晶体管的方法及其结构
公开(公告)号：US07745879B2
公开(公告)日：2010-06-29
申请号：US11872953
申请日：2007-10-16
申请人： Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
发明人： Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
IPC分类号： H01L29/43 , H01L29/786
CPC分类号： H01L29/78624 , H01L29/66772 , H01L29/78612
摘要： A method of fabricating a high voltage fully depleted silicon-on-insulator (FD SOI) transistor, the FD SOI transistor having a structure including a region within a body on which a gate structure is disposed. The region includes a channel separating the source region and the drain region. Above the source region is disposed a carrier recombination element, which abuts the gate structure and is electrically connected to the region via the channel. The drain region is lightly doped and ballasted to increase breakdown voltage. The FD SOI may be fabricated by forming a body with a thin silicon layer disposed on a buried oxide (BOX). Alternatively, the body may be formed using a partially depleted (PD) SOI where the region formed therein has a reduced thickness in comparison to the overall thickness of the PD SOI.
摘要翻译：一种制造高电压完全耗尽的绝缘体上硅（FD SOI）晶体管的方法，所述FD SOI晶体管具有包括在其中设置栅极结构的主体内的区域的结构。该区域包括分离源极区域和漏极区域的沟道。在源极区上方设置有载流子复合元件，该载流子复合元件邻接栅极结构，并且经由沟道电连接到该区域。漏极区域被轻掺杂并镇流以增加击穿电压。可以通过形成具有设置在掩埋氧化物（BOX）上的薄硅层的主体来制造FD SOI。或者，可以使用部分耗尽（PD）SOI形成主体，其中形成在其中的区域与PD SOI的总厚度相比具有减小的厚度。

149. 发明授权

US07692254B2 Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure 有权
标题翻译：具有合并源极/漏极硅化物的鳍型场效应晶体管结构和形成结构的方法
公开(公告)号：US07692254B2
公开(公告)日：2010-04-06
申请号：US11778217
申请日：2007-07-16
申请人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.
摘要翻译：这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的实施例，其中多个散热片部分或完全由高导电材料（例如，金属硅化物）。以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。

150. 发明申请

US20090302402A1 MUGFET WITH STUB SOURCE AND DRAIN REGIONS 有权
标题翻译： MUFAET与STUB源和排水区域
公开(公告)号：US20090302402A1
公开(公告)日：2009-12-10
申请号：US12132865
申请日：2008-06-04
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/00 , H01L21/8236
CPC分类号： H01L29/785 , H01L29/66803
摘要： The present invention provides a semiconductor device that includes at least one semiconductor Fin structure atop the surface of a substrate; the semiconducting fin structure including a channel of a first conductivity type and source/drain regions of a second conductivity type, the source/drain regions present at each end of the semiconductor fin structure; a gate structure immediately adjacent to the semiconductor fin structure, a dielectric spacer abutting each sidewall of the gate structure wherein the each end of the fin structure extends a dimension that is less than about ¼ a length of the Si-containing fin structure from a sidewall of the dielectric spacer; and a semiconductor region to the each end of the semiconductor fin structure, wherein the semiconductor region to the each end of the semiconductor fin structure is separated from the gate structure by the dielectric spacer.
摘要翻译：本发明提供一种半导体器件，其包括在衬底的表面上方的至少一个半导体鳍结构; 所述半导体鳍结构包括第一导电类型的沟道和第二导电类型的源极/漏极区，所述源/漏区存在于所述半导体鳍结构的每个端部处; 靠近半导体鳍片结构的栅极结构，邻接栅极结构的每个侧壁的电介质间隔物，其中鳍状结构的每个端部从侧壁延伸小于约含有Si的鳍结构的长度的尺寸的电介质间隔物; 以及到半导体鳍片结构的每一端的半导体区域，其中半导体鳍片结构的每个端部的半导体区域通过电介质间隔物与栅极结构分离。

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