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131. 发明授权

US11115055B2 Method and apparatus for encoding and decoding data in memory system 有权
公开(公告)号：US11115055B2
公开(公告)日：2021-09-07
申请号：US16244944
申请日：2019-01-10
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Ariel Doubchak , Dikla Shapiro , Amit Berman
IPC分类号： H04L1/00 , H03M13/15 , H03M13/29 , G06F3/06 , H03M13/09 , G06F11/10
摘要： A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a Syndrome stage for generating syndromes based on a BCH encoded word, a Berlekamp-Massey (BM) stage performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients, a Chien stage that performs a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) to generate error bits and iteration information, and a Frame Fixer stage configured to reorder the error bits to be sequential based on the iteration information. The BCH decoder decodes the BCH encoded word using the reordered error bits.

132. 发明授权

US11101823B2 Memory system 有权
公开(公告)号：US11101823B2
公开(公告)日：2021-08-24
申请号：US16727648
申请日：2019-12-26
申请人： KIOXIA Corporation
发明人： Yasuyuki Imaizumi , Satoshi Shoji , Mitsunori Tadokoro , Takashi Ishiguro , Yifan Tang
IPC分类号： H03M13/29 , G06F11/10 , H03M13/11 , H03M13/37 , G06F11/30
摘要： A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.

133. 发明授权

US11095313B2 Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures 有权
公开(公告)号：US11095313B2
公开(公告)日：2021-08-17
申请号：US16659241
申请日：2019-10-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Robert Montoye , Jeffrey Derby , Bruce Fleischer , Prashant Jayaprakash Nair
IPC分类号： H03M13/00 , H03M13/29 , G06F11/07 , H03M13/09 , H03M13/19
摘要： Single error correction (“SEC”) code and triple error detection (“TED”) code are used to optimize bandwidth and resilience under multiple bit failures. One or more errors in data stored in duplicated registers are detected and corrected using the SEC code and TED code where simultaneous read operations are produced with two copies of data for each of the duplicated registers for a multi-port banked memory array. The SEC code and TED code may be included in each of the two data copies of the simultaneous read operations.

134. 发明授权

US11088713B1 Solid state drive implementing a rate-compatible polar code 有权
公开(公告)号：US11088713B1
公开(公告)日：2021-08-10
申请号：US16748002
申请日：2020-01-21
申请人： Diego Melloni
发明人： Diego Melloni
IPC分类号： H03M13/00 , H03M13/45 , H03M13/13 , H03M13/21 , H03M13/29
摘要： A method for extending a polar code by determining an extension number E such that E/2

135. 发明授权

US11075654B2 Method and error correction system for correcting an error at a unit position of a received signal 有权
公开(公告)号：US11075654B2
公开(公告)日：2021-07-27
申请号：US16870732
申请日：2020-05-08
申请人： I SHOU UNIVERSITY
发明人： Yao-Tsu Chang , Chong-Dao Lee
IPC分类号： H03M13/00 , H03M13/29 , H03M13/15
摘要： A method for correcting an error of a received signal is provided. The method includes: determining a target degree based upon a length of the received signal; obtaining plural primitive polynomials each having a degree equal to the target degree; selecting one of the primitive polynomials as a target polynomial; defining plural syndromes according to the received signal; generating a group of product values based on the syndromes; obtaining plural coefficient polynomials based on the product values; obtaining monomial trace coefficients based on the coefficient polynomials; generating an error correction value based on the monomial trace coefficients; and correcting the error based on the error correction value.

136. 发明申请

US20210226648A1 SOLID STATE DRIVE IMPLEMENTING A RATE-COMPATIBLE POLAR CODE 有权
公开(公告)号：US20210226648A1
公开(公告)日：2021-07-22
申请号：US16748002
申请日：2020-01-21
申请人： Diego Melloni
发明人： Diego Melloni
IPC分类号： H03M13/00 , H03M13/45 , H03M13/29 , H03M13/21 , H03M13/13
摘要： 1. A method comprising: receiving input data including an array of information bits in a number equal to a first number, and encoding, through a polar code, said input data into a codeword having an array of codeword bits in a number equal to a second number, the codeword bits including said information bits and a plurality of frozen bits; wherein said encoding comprises: determining a third number as the lowest power of two number that is higher than said second number; accessing an information content indicative of a bit unreliability associated with each bit position in said array of codeword bits; selecting, among the bit positions in the information content, the bit positions associated with a number of highest bit unreliabilities equal to a fourth number, to obtain selected bit positions, said fourth number being equal to a difference between the third number and the second number; determining extended input data by adding to the input data a number of redundant bits equal to said fourth number, wherein said adding comprises adding, in the input data, the number of redundant bits in the respective selected bit positions; through the polar code, encoding the extended input data and a number of frozen bits equal to a difference between the second number and the first number, thereby obtaining an extended codeword including said codeword; wherein the method further comprises, after said decoding, deleting said added number of redundant bits in order to obtain output data corresponding to the input data.

137. 发明授权

US11069403B2 Semiconductor storage device and memory system 有权
公开(公告)号：US11069403B2
公开(公告)日：2021-07-20
申请号：US16783575
申请日：2020-02-06
申请人： TOSHIBA MEMORY CORPORATION
发明人： Masanobu Shirakawa , Takayuki Akamine
IPC分类号： G06F11/10 , G11C29/52 , G11C11/56 , H03M13/29 , G11C16/04 , G11C16/34 , G11C29/04
摘要： According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.

138. 发明授权

US11063612B1 Parallelizing encoding of binary symmetry-invariant product codes 有权
公开(公告)号：US11063612B1
公开(公告)日：2021-07-13
申请号：US16806387
申请日：2020-03-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Robert Allan Cyprus , Charles Camp
IPC分类号： H03M13/29
摘要： An encoder encodes input data utilizing a binary symmetry-invariant product code including D data bits and P parity bits in each dimension. The encoder includes a half-size data array including K subarrays each having multiple rows of storage for H bits of data, where D is an integer equal to 2×H+1 and K is an integer that is 2 or greater. The encoder is configured to access K rows of data by reading a respective H-bit data word of input data from each of the multiple subarrays and K H-bit data words of duplicate data from across multiple different rows of the subarrays. The encoder further includes at least one register configured to receive the bits read from the half-size data array code and rotate them as needed, at least one row parity generator, and a column parity generator that generates column parities based on row parity.

139. 再颁专利

USRE48627E1 Method of processing traffic information and digital broadcast system 有权
公开(公告)号：USRE48627E1
公开(公告)日：2021-07-06
申请号：US16260646
申请日：2019-01-29
申请人： LG ELECTRONICS INC.
发明人： Jin Pil Kim , Young In Kim , Ho Taek Hong , In Hwan Choi , Kook Yeon Kwak , Hyoung Gon Lee , Byoung Gill Kim , Jin Woo Kim , Won Gyu Song , Jong Moon Kim
IPC分类号： H03M13/29 , H04H20/55 , H04H20/95 , H04L1/00
摘要： A digital broadcast transmitting/receiving system and a method for processing data are disclosed. The method for processing data may enhance the receiving performance of the receiving system by performing additional coding and multiplexing processes on the traffic information data and transmitting the processed data. Thus, robustness is provided to the traffic information data, thereby enabling the data to respond strongly against the channel environment which is always under constant and vast change.

140. 发明授权

US11057056B2 Transmitting apparatus and interleaving method thereof 有权
公开(公告)号：US11057056B2
公开(公告)日：2021-07-06
申请号：US16442339
申请日：2019-06-14
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Hong-sil Jeong , Kyung-joong Kim , Se-ho Myung
IPC分类号： H03M13/00 , H03M13/27 , H04L1/00 , H03M13/25 , H03M13/29 , H03M13/11 , H03M13/15
摘要： A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a Low Density Parity Check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a plurality of modulation symbols, wherein the modulator is configured to map bits included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of each of the modulation symbols.

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