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131. 发明申请

US20020188783A1 Fly-by serial bus arbitration 有权
标题翻译：飞行串行总线仲裁
公开(公告)号：US20020188783A1
公开(公告)日：2002-12-12
申请号：US10136168
申请日：2002-04-30
申请人： Apple Computer, Inc.
发明人： William S. Duckwall , Michael D. Teener
IPC分类号： G06F013/38
CPC分类号： H04L12/40058 , H04L12/40084 , H04L12/40136 , H04L12/417 , H04L29/06 , H04L69/18 , H04L69/323 , H04L69/324
摘要： In a first embodiment, multi-speed concatenated packet strings are transmitted by a first node on a serial bus. To accommodate multi-speed packets, a speed signal is transmitted immediately prior to the packet. In a second embodiment, ACK-concatenation is used to allow a node to transmit a data packet immediately after transmitting an acknowledge signal on the bus. The data packet need not be related to the ACK packet. In a third embodiment, a node which receives a first data packet followed by a data end signal on a child port, concatenates a second data packet onto the first data packet during retransmission. The second data packet is also transmitted down the bus in the direction of the node which originally transmitted the first data packet.
摘要翻译：在第一实施例中，多速串联分组串由串行总线上的第一节点发送。为了适应多速分组，在分组之前立即发送速度信号。在第二实施例中，使用ACK级联来允许节点在总线上发送确认信号之后立即发送数据分组。数据包不需要与ACK包相关。在第三实施例中，在子端口接收第一数据分组后跟数据结束信号的节点在重传期间将第二数据分组连接到第一数据分组上。第二数据分组也沿着最初发送第一数据分组的节点的方向沿总线发送。

132. 发明授权

US06356558B1 Arbitration techniques for a high speed serial bus 失效
标题翻译：用于高速串行总线的仲裁技术
公开(公告)号：US06356558B1
公开(公告)日：2002-03-12
申请号：US09017425
申请日：1998-02-02
申请人： Jerrold V. Hauck , David W. LaFollette
发明人： Jerrold V. Hauck , David W. LaFollette
IPC分类号： H04J326
CPC分类号： H04L12/40071 , H04L12/40084 , H04L12/44
摘要： A method and apparatus of improving serial bus efficiency. Improvement of bus efficiency through the reduction of enforced subaction gaps can be accomplished by attaching an explicit end of subaction (EOS) token to packets that are the last packet of a subaction. The EOS should be selected to be an encoding that is not easily confused with any encoding used for normal data encoding. The presence of the EOS token permits arbitration to begin without waiting for a subaction gap after the EOS token is seen on the bus. Additionally, it permits fly by concatenation with packets containing an EOS token. In some cases multiple concatenations are possible. Because the EOS token is independent of subaction type, this technique expands readily as new subactions are developed. Employing the features overall bus efficiency can be increased.
摘要翻译：一种提高串行总线效率的方法和装置。通过减少强制的分工差距来提高总线效率可以通过将子操作（EOS）令牌的显式结束附加到作为子操作的最后一个数据包的数据包来实现。 EOS应被选择为不容易与用于正常数据编码的编码混淆的编码。 EOS令牌的存在允许仲裁开始，而不必在总线上看到EOS令牌之后等待分工差距。此外，它允许通过与包含EOS令牌的数据包连接来进行飞行。在某些情况下，可能会有多个连接。由于EOS令牌独立于子操作类型，因此随着新的子动作的开发，这种技术随着扩展。采用整体总线效能的特点可以增加。

133. 发明授权

US06324611B1 Physical layer interface and method for arbitration over serial bus using digital line state signals 失效
标题翻译：物理层接口和方法用串行总线仲裁使用数字线路状态信号
公开(公告)号：US06324611B1
公开(公告)日：2001-11-27
申请号：US09154980
申请日：1998-09-17
申请人： Takayuki Nyu
发明人： Takayuki Nyu
IPC分类号： G06F1300
CPC分类号： H04L12/40084
摘要： A physical layer interface for a serial bus includes a controller for producing parallel data representing a near-end line state of the serial bus. A line transmitter is connected to the controller for converting the parallel data therefrom into serial data and transmitting the serial data to the serial bus. A line receiver is connected to the serial bus for receiving therefrom serial dtaa and converting the received serial data into parallel data representing a far-end line state of the serial bus. A differential line state of the serial bus is detected from the parallel data of the controller and the parallel data of the line receiver. The detected differential line state is the input to the controller. In a modified embodiment, a far-end line state of the serial bus is detected from the near-end line state of the serial bus and a far-end differential signal received by the line receiver and directly supplied to the controller. A differential line state of the serial bus is then detected using the near-end line state and the detected far-end line state and serial data representing the detected diffrential line state is sent through the line transmitter.
摘要翻译：用于串行总线的物理层接口包括用于产生表示串行总线的近端线路状态的并行数据的控制器。线路发射器连接到控制器，用于将并行数据转换成串行数据并将串行数据发送到串行总线。线路接收器连接到串行总线，用于从串行总线接收串行数据，并将接收到的串行数据转换为表示串行总线远端线路状态的并行数据。从控制器的并行数据和线路接收器的并行数据中检测串行总线的差分线路状态。检测到的差分线路状态是控制器的输入。在修改实施例中，串行总线的远端线状态从串行总线的近端线路状态和由线路接收器接收的直接提供给控制器的远端差分信号进行检测。然后使用近端线路状态检测串行总线的差分线路状态，并且检测到的远端线路状态，并且通过线路发送器发送表示检测到的不同线路状态的串行数据。

134. 发明授权

US5946298A Digital interface which inserts a transfer rate value into a packet header and controls access to a bus based on a total transfer rate 失效
标题翻译：数字接口，其将传输速率值插入到分组报头中，并且基于总传输速率控制对总线的访问
公开(公告)号：US5946298A
公开(公告)日：1999-08-31
申请号：US626143
申请日：1996-04-05
申请人： Takehiko Okuyama
发明人： Takehiko Okuyama
IPC分类号： G06F13/362 , G11B20/12 , G11B27/032 , G11B27/10 , H04J3/00 , H04L12/40 , H04L12/64 , H04N5/92 , H04N7/173 , H04N9/804 , H04N19/00 , H04N19/423 , H04N19/65 , H04N19/70 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26
CPC分类号： H04L12/40058 , G11B20/1205 , G11B27/032 , G11B27/10 , H04L12/40084 , H04N7/173 , H04N9/8042
摘要： A transfer-rate computing component computes a transfer rate of an output from a digital video tape recorder component to output the same through a packet conversion component. Child units, which are newly connected to a bus, output data of the transfer rate subsequent to a request command of a bus use right. A total transfer-rate computing component of a parent unit computes a total transfer rate of the data which are transmitted through the bus. An arbitration control part judges whether or not the total transfer rate exceed the maximum transfer rate which is set in the bus. Only when the total transfer rate does not exceed the maximum transfer rate, a command transmission component issues a bus use permission right, to accept the transmission of data from newly connected child units. In this manner, when a new unit or device is connected to the bus and also when connection of the bus is turned off, synchronous transfer is assured.
摘要翻译：传输速率计算部件计算来自数字磁带录像机部件的输出的传送速率，以通过分组转换部件输出。新连接到总线的子单元在总线使用权的请求命令之后输出传输速率的数据。母单元的总转移率计算组件计算通过总线传输的数据的总传输速率。仲裁控制部分判断总传输速率是否超过总线中设置的最大传输速率。仅当总传输速率不超过最大传输速率时，命令传输组件发出总线使用许可权，接受来自新连接的子单元的数据传输。以这种方式，当新的单元或设备连接到总线时，并且当总线的连接被关闭时，确保同步传输。

135. 发明授权

US5886983A Data bus system with resource control compensating for limited transmission capacity 失效
标题翻译：具有资源控制的数据总线系统补偿有限的传输容量
公开(公告)号：US5886983A
公开(公告)日：1999-03-23
申请号：US664071
申请日：1996-06-13
申请人： Thomas A. H. M. Suters , Ronald W. J. J. Saeijs , Rudolf H. J. Bloks , Jurgen F. Rosengren
发明人： Thomas A. H. M. Suters , Ronald W. J. J. Saeijs , Rudolf H. J. Bloks , Jurgen F. Rosengren
IPC分类号： H04L12/28 , H04J3/14 , H04L12/40 , H04L12/403 , H04L12/44 , H04L12/64 , H04L29/06 , H04L29/08 , H04Q11/00 , H04Q11/02
CPC分类号： H04L12/40058 , H04L12/40065 , H04L12/40084 , H04L12/403 , H04L12/44 , H04L29/06 , H04L67/1097 , H04L69/08 , H04L69/329
摘要： A data bus system has a number of stations which are interconnected via a bus. The bus has a limited data transmission capacity available. From a transmitter station a resource control station reads which part of the available transmission capacity is required for the relevant transmitter. The resource control station allocates the required transmission capacity to the relevant transmitter station if adequate transmission capacity is available. Only if adequate transmission capacity is available is transmission by the relevant transmitter station enabled.
摘要翻译：数据总线系统具有通过总线互连的多个站。总线数据传输容量有限。资源控制站从发射台读取相关发射机所需的可用传输容量的哪一部分。如果有足够的传输容量可用，资源控制站将所需的传输容量分配给相关的发射机站。只有有足够的传输容量才能使能相关发射台的传输。

136. 发明授权

US5859985A Arbitration controller for providing arbitration on a multipoint high speed serial bus using drivers having output enable pins 失效
标题翻译：仲裁控制器，用于使用具有输出使能引脚的驱动器在多点高速串行总线上提供仲裁
公开(公告)号：US5859985A
公开(公告)日：1999-01-12
申请号：US824937
申请日：1997-03-26
申请人： Eamonn Gormley , James M. Hite , Chad A. Pralle
发明人： Eamonn Gormley , James M. Hite , Chad A. Pralle
IPC分类号： G06F3/00 , G06F13/36 , G06F13/362 , H04L12/40 , H04L12/403 , H04L12/64
CPC分类号： H04L12/40084 , G06F13/36
摘要： An arbitration controller provides arbitration on a multipoint, high speed serial bus with a plurality of drivers. Each driver includes a data input pin, an output enable pin, and an output pin. The bus defaults to a first state when the output of the plurality of drivers are set to high impedance. The arbitration controller eliminates any unstable output states on the drivers by controlling the input signals on the drivers. The arbitration controller detects when the bus is in an arbitration mode. When this is detected, the arbitration controller inputs data to the output enable pin and inputs an opposite state of the first state to the data input pin. Further, the arbitration controller detects when the bus is in a data mode. When this is detected, the arbitration controller inputs data to the data input pin and inputs a driver control signal to the output enable pin.
摘要翻译：仲裁控制器在具有多个驱动器的多点高速串行总线上提供仲裁。每个驱动器包括一个数据输入引脚，一个输出使能引脚和一个输出引脚。当多个驱动器的输出被设置为高阻抗时，总线默认为第一状态。仲裁控制器通过控制驱动器上的输入信号来消除驱动器上的任何不稳定的输出状态。仲裁控制器检测总线何时处于仲裁模式。当检测到这种情况时，仲裁控制器将数据输入到输出使能引脚，并将第一状态的相反状态输入到数据输入引脚。此外，仲裁控制器检测总线何时处于数据模式。当检测到这种情况时，仲裁控制器将数据输入到数据输入引脚，并将驱动器控制信号输入到输出使能引脚。

137. 发明授权

US5495481A Method and apparatus for accelerating arbitration in a serial bus by detection of acknowledge packets 失效
标题翻译：通过确认数据包的检测来加速串行总线仲裁的方法和装置
公开(公告)号：US5495481A
公开(公告)日：1996-02-27
申请号：US316552
申请日：1994-09-30
申请人： William S. Duckwall
发明人： William S. Duckwall
IPC分类号： G06F13/36 , G06F13/368 , H04L12/40 , H04L12/64 , H04J3/26
CPC分类号： H04L12/40084 , G06F13/36 , G06F13/368
摘要： Methods and circuitry for arbitrating for control of a serial bus are described. According to one embodiment, one or more nodes of a serial bus are provided with a mechanism for discriminating between data packets and acknowledge packets. If a packet transmitted, repeated, or received by the node is a data packet, the node remains idle for a subaction gap time T.sub.sa to better ensure that the expected acknowledge packet is allowed to successfully propagate throughout the serial bus to the source node. If the packet transmitted by the node is an acknowledge packet, the node is free to begin the arbitration phase of the next subaction if there are no other conditions that prevent further arbitration by that node. To discriminate between data packets and acknowledge packets, a counter is used to determine the length of a transmitted packet, and the length is compared to the expected length of an acknowledge packet. If the length is equal to the expected length of an acknowledge packet, the packet is an acknowledge packet.
摘要翻译：描述用于串行总线控制的仲裁的方法和电路。根据一个实施例，串行总线的一个或多个节点被提供有用于区分数据分组和确认分组的机制。如果由节点发送，重复或接收的分组是数据分组，则节点保持空闲以用于子动作间隙时间Tsa，以更好地确保允许期望的确认分组在整个串行总线中成功传播到源节点。如果节点发送的分组是确认分组，则如果没有其他条件阻止该节点的进一步仲裁，则节点可以自由地开始下一个分组的仲裁阶段。为了区分数据分组和确认分组，使用计数器来确定发送分组的长度，并将长度与确认分组的预期长度进行比较。如果长度等于确认分组的预期长度，则分组是确认分组。

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