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131. 发明申请

US20170012001A1 SELF-ALIGNED BARRIER AND CAPPING LAYERS FOR INTERCONNECTS 审中-公开
标题翻译：用于互连的自对准障碍物和捕获层
公开(公告)号：US20170012001A1
公开(公告)日：2017-01-12
申请号：US15207198
申请日：2016-07-11
申请人： President and Fellows of Harvard College
发明人： Roy Gerald GORDON , Harish B. BHANDARI , Yeung AU , Youbo LIN
IPC分类号： H01L23/532 , H01L21/285 , H01L23/522 , H01L21/288 , H01L21/768 , H01L23/528
CPC分类号： H01L23/53238 , C23C16/18 , C23C16/34 , C23C16/401 , H01L21/28506 , H01L21/28556 , H01L21/28562 , H01L21/288 , H01L21/2885 , H01L21/76814 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L21/76843 , H01L21/76849 , H01L21/76853 , H01L21/76862 , H01L21/76867 , H01L21/76871 , H01L21/76873 , H01L21/76874 , H01L21/76876 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing layer forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The Mn, Cr, or V containing layer also promotes strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use, as well as protecting against failure by electromigration of the copper during use of the devices and protecting the copper from corrosion by oxygen or water from its surroundings. In forming such integrated circuits, certain embodiments of the invention provide methods to selectively deposit Mn, Cr, V, or Co on the copper surfaces while reducing or even preventing deposition of Mn, Cr, V, or Co on insulator surfaces. Catalytic deposition of copper using a Mn, Cr, or V containing precursor and an iodine or bromine containing precursor is also provided.
摘要翻译：提供了一种用于集成电路中铜线集成电路的互连结构及其制造方法。含有Mn，Cr或V的层形成了阻碍铜从电线中扩散的阻挡层，从而保护绝缘体免于过早击穿，并保护晶体管免受铜的退化。含Mn，Cr或V的层还促进了铜和绝缘体之间的强粘附，从而在制造和使用过程中保持了器件的机械完整性，并且在使用器件期间防止铜的电迁移失效，并保护铜从其周围的氧气或水中腐蚀。在形成这样的集成电路中，本发明的某些实施例提供了在铜表面上选择性地沉积Mn，Cr，V或Co的方法，同时减少或甚至防止在绝缘体表面上沉积Mn，Cr，V或Co。还提供了使用含有Mn，Cr或V的前体和含碘或溴的前体的铜的催化沉积。

132. 发明申请

US20160380042A1 Passive Chip Device and Method of Making the Same 有权
标题翻译：被动芯片器件及其制作方法
公开(公告)号：US20160380042A1
公开(公告)日：2016-12-29
申请号：US15152882
申请日：2016-05-12
申请人： Wafer Mems Co., LTD.
发明人： Min-Ho Hsiao , Pang-Yen Lee , Yen-Hao Tseng
IPC分类号： H01L49/02 , H01L23/12 , H01L23/528 , H01L21/768
CPC分类号： H01L28/10 , H01F17/0033 , H01F17/02 , H01F27/292 , H01F41/04 , H01F41/041 , H01F41/046 , H01F2017/004 , H01L21/76871 , H01L23/645
摘要： A passive chip device includes a chip body, a conductive coil and a surface-mount contact unit. The chip body is in the form of a single piece, and has two opposite end faces and a first surface which is between the end faces. The conductive coil is deposited on and surrounding the chip body. The surface-mount contact unit includes two spaced apart conductive terminal contacts. Each of the terminal contacts extends from a respective one of the end faces to the first surface and connects to a respective one of end portions of the coil. The method of making the passive chip device is also disclosed.
摘要翻译：无源芯片器件包括芯片体，导电线圈和表面安装接触单元。芯片体为单件形式，具有两个相对端面和位于端面之间的第一表面。导电线圈沉积在芯片本体周围。表面安装接触单元包括两个间隔开的导电端子触点。每个端子触头从相应的一个端面延伸到第一表面并且连接到线圈的相应的一个端部。还公开了制造无源芯片器件的方法。

133. 发明授权

US09514983B2 Cobalt based interconnects and methods of fabrication thereof 有权
标题翻译：基于钴的互连及其制造方法
公开(公告)号：US09514983B2
公开(公告)日：2016-12-06
申请号：US13730184
申请日：2012-12-28
申请人： Christopher J. Jezewski , James S. Clarke , Tejaswi K. Indukuri , Florian Gstrein , Daniel J. Zierath
发明人： Christopher J. Jezewski , James S. Clarke , Tejaswi K. Indukuri , Florian Gstrein , Daniel J. Zierath
IPC分类号： H01L23/52 , H01L21/768 , H01L23/522 , H01L23/485 , H01L23/532
CPC分类号： H01L21/76841 , H01L21/288 , H01L21/76843 , H01L21/76847 , H01L21/76871 , H01L21/76877 , H01L21/76879 , H01L21/76883 , H01L23/485 , H01L23/5226 , H01L23/53261 , H01L23/53266 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A metal interconnect comprising cobalt and method of forming a metal interconnect comprising cobalt are described. In an embodiment, a metal interconnect comprising cobalt includes a dielectric layer disposed on a substrate, an opening formed in the dielectric layer such that the substrate is exposed. The embodiment further includes a seed layer disposed over the substrate and a fill material comprising cobalt formed within the opening and on a surface of the seed layer.
摘要翻译：描述了包括钴的金属互连和形成包含钴的金属互连的方法。在一个实施例中，包括钴的金属互连包括设置在基板上的电介质层，形成在电介质层中的开口，使得基板被暴露。该实施例还包括设置在基板上的种子层和在开口内和种子层的表面上形成的包含钴的填充材料。

134. 发明申请

US20160322255A1 METHOD FOR DEPOSITING A DIFFUSION BARRIER LAYER AND A METAL CONDUCTIVE LAYER 有权
标题翻译：用于沉积扩散障碍层和金属导电层的方法
公开(公告)号：US20160322255A1
公开(公告)日：2016-11-03
申请号：US15206112
申请日：2016-07-08
申请人： Applied Materials, Inc.
发明人： Tony CHIANG , Gongda YAO , Peijun DING , Fusen E. CHEN , Barry L. CHIN , Gene Y. KOHARA , Zheng XU , Hong ZHANG
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , C23C14/046 , C23C14/165 , H01L21/2855 , H01L21/76805 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865 , H01L21/76871 , H01L21/76877 , H01L21/76879 , H01L21/76883
摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.
摘要翻译：我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻的材料层的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染。使用传统的溅射或离子沉积溅射将第一保护层材料沉积在衬底表面上，结合足够低的衬底偏压，使得施加层的表面在保护层沉积期间不被腐蚀掉或被污染。随后，使用离子沉积溅射在增加的衬底偏压下施加雕刻的第二材料层，以从材料的第一保护层的一部分和第二沉积材料层的一部分雕刻出形状。该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层。

135. 发明授权

US09472377B2 Method and apparatus for characterizing metal oxide reduction 有权
标题翻译：用于表征金属氧化物还原的方法和装置
公开(公告)号：US09472377B2
公开(公告)日：2016-10-18
申请号：US14657956
申请日：2015-03-13
申请人： Lam Research Corporation
发明人： Edward C. Opocensky , Tighe A. Spurlin , Jonathan D. Reid
IPC分类号： H01J37/32 , H01L21/66 , H01L21/768 , H01L21/324 , C23C8/12 , C23C8/80
CPC分类号： H01J37/32 , C23C8/12 , C23C8/80 , H01J37/32357 , H01L21/02068 , H01L21/02244 , H01L21/02255 , H01L21/324 , H01L21/6719 , H01L21/6723 , H01L21/76855 , H01L21/76862 , H01L21/76871 , H01L21/76873 , H01L21/76876 , H01L22/14 , H01L22/20 , H01L22/26
摘要： Method and apparatus for characterizing metal oxide reduction using metal oxide films formed in an anneal chamber are disclosed. Oxygen is provided into an anneal chamber. A substrate including a metal seed layer is exposed to the oxygen and exposed to a heated substrate support in the anneal chamber to form a metal oxide of the metal seed layer. The oxidized substrate can be stored for later use or transferred to a processing chamber for reducing the metal oxide to metal. The oxidized substrates formed in this manner provide metal oxides that are repeatable, uniform, and stable. The oxidized substrate is exposed to a reducing treatment under conditions that reduce the metal oxide to metal in the form of a film integrated with the metal seed layer.
摘要翻译：公开了使用在退火室中形成的金属氧化物膜来表征金属氧化物还原的方法和装置。氧被提供到退火室中。包含金属种子层的基板暴露于氧气并暴露于退火室中加热的基板支撑件，以形成金属种子层的金属氧化物。氧化的底物可以储存以供以后使用或转移到处理室以将金属氧化物还原成金属。以这种方式形成的氧化衬底提供可重复，均匀和稳定的金属氧化物。在将金属氧化物还原为与金属种子层结合的膜形式的金属的条件下，将氧化的基板暴露于还原处理。

136. 发明授权

US09466533B2 Semiconductor structure including a through electrode, and method for forming the same 有权
公开(公告)号：US09466533B2
公开(公告)日：2016-10-11
申请号：US14833368
申请日：2015-08-24
申请人： International Business Machines Corporation
发明人： Akihiro Horibe , Hiroyuki Mori , Yasumitsu Orii , Kuniaki Sueoka , Kazushige Toriyama
IPC分类号： H01L21/768 , H01L25/065 , H01L23/48 , H01L25/00 , H01L23/00 , H01L21/308 , H01L21/48 , H01L23/522
CPC分类号： H01L21/76898 , H01L21/308 , H01L21/486 , H01L21/76802 , H01L21/76805 , H01L21/76831 , H01L21/76843 , H01L21/76871 , H01L21/76879 , H01L23/481 , H01L23/5226 , H01L24/24 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/05009 , H01L2224/24011 , H01L2224/24051 , H01L2224/24145 , H01L2224/244 , H01L2224/2919 , H01L2224/32145 , H01L2224/82031 , H01L2224/82101 , H01L2224/9202 , H01L2224/92144 , H01L2224/92244 , H01L2225/06524 , H01L2225/06544 , H01L2225/06565 , H01L2924/10253 , H01L2924/14 , H01L2924/00014
摘要： A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned electrode parts, the electrode part on the surface of an uppermost layer and including an aperture, the electrode part of the intermediate layer having an aperture smaller than the aperture of the uppermost layer; a through-hole extending from the aperture of the electrode part on the uppermost layer to the surface of the electrode part on a lowermost layer, the through-hole having a depressed part on a side wall thereof between the electrode parts therein; an insulating layer disposed on the entire side wall in the through-hole at a part other than on surfaces of the electrode parts; and a conductive material filling the through-hole from the surface of the electrode part on the lowermost layer to the surface of the electrode part on the uppermost layer.

137. 发明授权

US09461057B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US09461057B2
公开(公告)日：2016-10-04
申请号：US14699611
申请日：2015-04-29
申请人： SK hynix Inc.
发明人： Young Jin Lee
IPC分类号： H01L27/115 , H01L21/768
CPC分类号： H01L27/115 , H01L21/76802 , H01L21/76843 , H01L21/76871 , H01L21/76877 , H01L21/76879 , H01L27/11556 , H01L27/11582
摘要： A semiconductor device may include semiconductor patterns. The semiconductor device may include insulating layers including first regions surrounding the semiconductor patterns and second regions isolated from each other by island-type first openings and connecting the first regions adjacent to each other. The semiconductor device may include metal layers interposed between the first regions of the stacked insulating layers surrounding the semiconductor patterns, and isolated from each other by line-type second openings overlapping the first openings and the second regions. The semiconductor device may include dielectric patterns partially interposed between the insulating layers and the metal layers and exposed through the second openings.
摘要翻译：半导体器件可以包括半导体图案。半导体器件可以包括绝缘层，其包括围绕半导体图案的第一区域和通过岛状第一开口彼此隔离并且连接彼此相邻的第一区域的第二区域。半导体器件可以包括介于包围半导体图案的层叠绝缘层的第一区域之间的金属层，并且通过与第一开口和第二区域重叠的线型第二开口彼此隔离。半导体器件可以包括部分插入在绝缘层和金属层之间并且通过第二开口暴露的电介质图案。

138. 发明授权

US09397045B2 Structure and formation method of damascene structure 有权
标题翻译：镶嵌结构的结构和形成方法
公开(公告)号：US09397045B2
公开(公告)日：2016-07-19
申请号：US14516222
申请日：2014-10-16
申请人： Taiwan Semiconductor Manufacturing Co., Ltd
发明人： Tai-Yen Peng , Chia-Tien Wu , Jye-Yen Cheng
IPC分类号： H01L21/76 , H01L23/532 , H01L21/768 , H01L23/528
CPC分类号： H01L21/76897 , H01L21/76805 , H01L21/76807 , H01L21/7681 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/7684 , H01L21/76843 , H01L21/76852 , H01L21/76871 , H01L21/76877 , H01L21/76885 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53209 , H01L23/53238 , H01L23/53242 , H01L23/53257 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first conductive feature over the semiconductor substrate. The semiconductor device also includes a first dielectric layer over the semiconductor substrate and surrounding the first conductive feature. The semiconductor device further includes a second conductive feature over the first conductive feature, and the second conductive feature extends into the first conductive feature. In addition, the semiconductor device includes a second dielectric layer over the first dielectric layer and surrounding the second conductive feature.
摘要翻译：提供了半导体器件的结构和形成方法。半导体器件包括半导体衬底和半导体衬底上的第一导电特征。半导体器件还包括半导体衬底上的第一电介质层并且围绕第一导电特征。半导体器件还包括在第一导电特征上的第二导电特征，并且第二导电特征延伸到第一导电特征中。此外，半导体器件包括位于第一介电层上并包围第二导电特征的第二电介质层。

139. 发明授权

US09396992B2 Method of using a barrier-seed tool for forming fine-pitched metal interconnects 有权
标题翻译：使用阻挡种子工具形成细间距金属互连的方法
公开(公告)号：US09396992B2
公开(公告)日：2016-07-19
申请号：US14196268
申请日：2014-03-04
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ya-Lien Lee
IPC分类号： H01L21/768
CPC分类号： H01L21/76862 , H01J37/32422 , H01J37/32706 , H01L21/02063 , H01L21/02068 , H01L21/32136 , H01L21/76802 , H01L21/7681 , H01L21/76814 , H01L21/76816 , H01L21/7684 , H01L21/76843 , H01L21/76865 , H01L21/76871 , H01L21/76873 , H01L21/76879 , H01L23/5226 , H01L23/528 , H01L23/53238
摘要： A barrier seed tool is configured to clean trenches in a first chamber, line the trenches with a diffusion barrier layer, and form a copper seed layer over the diffusion barrier layer in a second chamber. The clean chamber is configured to reduce overhangs in the copper seed layer by producing a plasma comprising positively and negatively charged ions including halogen ions, filtering the plasma to selectively exclude positively charged ions, and bombarding with the filtered plasma. The tool and related method can be used to reduce overhangs and improve subsequent gap fill while avoiding excessive damage to the dielectric matrix.
摘要翻译：阻挡种子工具被配置为清洁第一室中的沟槽，将沟槽与扩散阻挡层对准，并在第二室中在扩散阻挡层上形成铜籽晶层。清洁室被配置为通过产生包括正离子和带负电荷的离子包括卤素离子，过滤等离子体以选择性地排除带正电荷的离子和用过滤的等离子体轰击来减少铜籽晶层中的突出端。该工具和相关方法可用于减少悬垂并改善随后的间隙填充，同时避免对电介质基体的过度损坏。

140. 发明申请

US20160181154A1 SEMICONDUCTOR DEVICE WITH MULTI-LAYER METALLIZATION 审中-公开
标题翻译：具有多层金属化的半导体器件
公开(公告)号：US20160181154A1
公开(公告)日：2016-06-23
申请号：US15054318
申请日：2016-02-26
申请人： Infineon Technologies AG
发明人： Matthias Stecher
IPC分类号： H01L21/768 , H01L23/528 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5283 , H01L21/2885 , H01L21/32051 , H01L21/76807 , H01L21/76838 , H01L21/7685 , H01L21/76852 , H01L21/76871 , H01L21/76873 , H01L21/76879 , H01L21/76885 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： One or more embodiments are related to a semiconductor device, comprising: a metallization layer comprising a plurality of portions, each of the portions having a different thickness. The metallization layer may be a final metal layer.
摘要翻译：一个或多个实施例涉及半导体器件，包括：包括多个部分的金属化层，每个部分具有不同的厚度。金属化层可以是最终的金属层。

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