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131. 发明申请

US20130272056A1 Apparatus for SRAM Cells 有权
标题翻译： SRAM单元设备
公开(公告)号：US20130272056A1
公开(公告)日：2013-10-17
申请号：US13446220
申请日：2012-04-13
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： G11C11/00
CPC分类号： H01L27/1104 , G11C8/14 , G11C11/412 , H01L27/0207 , H01L29/785
摘要： A memory cell comprises a first word line in a first interconnect layer, a first VSS line, a first bit line, a power source line, a second bit line and a second VSS line formed a second interconnect layer, a second word line in a third interconnect layer. The memory cell further comprises a word line strap structure formed between the power source line and the second bit line, wherein the word line strap structure couples the first word line and the second word line.
摘要翻译：存储单元包括第一互连层中的第一字线，第一VSS线，第一位线，电源线，第二位线和形成第二互连层的第二VSS线，第二字线第三互连层。存储单元还包括形成在电源线和第二位线之间的字线带结构，其中字线条结构将第一字线和第二字线耦合。

132. 发明授权

US08399935B2 Embedded SRAM memory for low power applications 有权
标题翻译：用于低功耗应用的嵌入式SRAM存储器
公开(公告)号：US08399935B2
公开(公告)日：2013-03-19
申请号：US12829084
申请日：2010-07-01
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L29/76
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1104
摘要： Circuits and methods for providing a dual gate oxide (DGO) embedded SRAM with additional logic portions, where the logic and the embedded SRAM have NMOS transistors having a common gate dielectric thickness but have different lightly doped drain (LDD) implantations formed using different LDD masks to provide optimum transistor operation. In an embodiment, a first embedded SRAM is a single port device and a second embedded SRAM is a dual port device having a separate read port. In certain embodiments, the second SRAM includes NMOS transistors having LDD implants formed using the logic portion LDD mask. Transistors formed with the logic portion LDD mask are faster and have lower Vt than transistors formed using a SRAM LDD mask. Dual core devices having multiple embedded SRAM arrays are disclosed. Methods for making the embedded SRAM are also disclosed.
摘要翻译：用于提供具有附加逻辑部分的双栅极氧化物（DGO）嵌入式SRAM的电路和方法，其中逻辑和嵌入式SRAM具有NMOS晶体管，其具有共同的栅极电介质厚度，但具有不同的LDD掩模形成的轻掺杂漏极（LDD）注入以提供最佳的晶体管操作。在一个实施例中，第一嵌入式SRAM是单端口设备，第二嵌入式SRAM是具有单独读取端口的双端口设备。在某些实施例中，第二SRAM包括具有使用逻辑部分LDD掩模形成的LDD注入的NMOS晶体管。与逻辑部分LDD掩模形成的晶体管比使用SRAM LDD掩模形成的晶体管更快，具有更低的Vt。公开了具有多个嵌入式SRAM阵列的双核心器件。还公开了制造嵌入式SRAM的方法。

133. 发明授权

US08258572B2 SRAM structure with FinFETs having multiple fins 有权
标题翻译：具有FinFET的SRAM结构具有多个鳍片
公开(公告)号：US08258572B2
公开(公告)日：2012-09-04
申请号：US12890132
申请日：2010-09-24
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L29/772
CPC分类号： H01L27/11 , H01L27/0207 , H01L27/1104 , H01L29/41791 , H01L29/785
摘要： A static random access memory (SRAM) cell includes a straight fin and a bended fin physically disconnected from the straight fin. The bended fin has a first portion and a second portion parallel to the straight fin. The distance between the first portion of the bended fin and the straight fin is smaller than the distance between the second portion of the bended fin and the straight fin. The SRAM cell includes a pull-down transistor including a portion of a first gate strip, which forms a first and a second sub pull-down transistor with the straight fin and the first portion of the bended fin, respectively. The SRAM cell further includes a pass-gate transistor including a portion of a second gate strip, which forms a first sub pass-gate transistor with the straight fin. The pull-down transistor includes more fins than the pass-gate transistor.
摘要翻译：静态随机存取存储器（SRAM）单元包括与直翅片物理断开的直翅片和弯曲的翅片。弯曲的翅片具有平行于直翅片的第一部分和第二部分。弯曲翅片的第一部分和直翅片之间的距离小于弯曲翅片的第二部分和直翅片之间的距离。 SRAM单元包括下拉晶体管，其包括第一栅极条的一部分，其分别与直鳍和弯曲鳍的第一部分形成第一和第二子下拉晶体管。 SRAM单元还包括一个包括第二栅极条的一部分的通过栅极晶体管，其形成具有直的鳍的第一子栅极晶体管。下拉晶体管包括比传输栅极晶体管更多的鳍片。

134. 发明授权

US07660149B2 SRAM cell with separate read and write ports 有权
标题翻译：具有单独读写端口的SRAM单元
公开(公告)号：US07660149B2
公开(公告)日：2010-02-09
申请号：US11636014
申请日：2006-12-07
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： This invention discloses a dual port static random access memory (SRAM) cell, which comprises at least one inverter coupled between a positive supply voltage (Vcc) and a complementary low supply voltage (Vss) and having an input and an output terminals, at least one PMOS transistor with its gate, source and drain connected to the output terminal, Vcc and input terminal, respectively, a write port connected to the input terminal and having a write-word-line, a write-enable and a write-bit-line, and a read port connected to either the input or output terminal and having a read-word-line and a read-bit-line.
摘要翻译：本发明公开了一种双端口静态随机存取存储器（SRAM）单元，其包括至少一个反相器，其耦合在正电源电压（Vcc）和互补低电源电压（Vss）之间，并且至少具有输入端和输出端一个PMOS晶体管，其栅极，源极和漏极分别连接到输出端子Vcc和输入端子，写入端口分别连接到输入端子并具有写入字线，写入使能和写入位线，线路和连接到输入或输出端子并具有读取字线和读取位线的读取端口。

135. 发明授权

US07606061B2 SRAM device with a power saving module controlled by word line signals 有权
标题翻译：具有由字线信号控制的省电模块的SRAM器件
公开(公告)号：US07606061B2
公开(公告)日：2009-10-20
申请号：US11835372
申请日：2007-08-07
申请人： Subramani Kengeri , Jhon-Jhy Liaw
发明人： Subramani Kengeri , Jhon-Jhy Liaw
IPC分类号： G11C11/00 , G11C5/06 , G11C7/10 , G11C5/14
CPC分类号： G11C11/412
摘要： An SRAM device include: a latch unit for retaining data; one or more pass gate transistors controlled by a word line for coupling the latch unit to a bit line and a complementary bit line; and a power saving module coupled to the latch unit for raising a source voltage of the latch unit in response to a control signal on the word line, thereby reducing a leakage current for the latch unit.
摘要翻译： SRAM装置包括：用于保留数据的锁存单元; 由字线控制的一个或多个传输门晶体管，用于将锁存单元耦合到位线和互补位线; 以及耦合到所述锁存单元的功率节省模块，用于响应于所述字线上的控制信号而提高所述锁存单元的源极电压，由此减小所述锁存单元的漏电流。

136. 发明授权

US07505354B2 Word line voltage control circuit for memory devices 有权
标题翻译：字线电压控制电路用于存储器件
公开(公告)号：US07505354B2
公开(公告)日：2009-03-17
申请号：US11502016
申请日：2006-08-10
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C11/417
摘要： A memory device includes at least one memory array having a plurality of memory cells addressed by a plurality of word lines and bit lines, and coupled between a power line and a ground line. A word line decoder is coupled to one end of the word line for selecting the word lines in response to input signals. A voltage control circuit is coupled to another end of the word line for connecting the word line to a ground voltage when the memory device is in a sleep mode, wherein the voltage control circuit is supplied by DC power.
摘要翻译：存储器件包括至少一个存储器阵列，其具有由多个字线和位线寻址的多个存储器单元，并且耦合在电力线和地线之间。字线解码器耦合到字线的一端，用于响应输入信号选择字线。当存储器件处于休眠模式时，电压控制电路耦合到字线的另一端，用于将字线连接到地电压，其中电压控制电路由直流电供给。

137. 发明授权

US07364961B2 SRAM cell design for soft error rate immunity 有权
标题翻译： SRAM单元设计，具有软错误率免疫
公开(公告)号：US07364961B2
公开(公告)日：2008-04-29
申请号：US11103754
申请日：2005-04-12
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L21/8244
CPC分类号： H01L27/11 , H01L27/1104
摘要： A new method to form a SRAM memory cell in an integrated circuit device is achieved. The method comprises providing a bi-stable flip-flop cell having a data storage node and a data bar storage node. A first capacitor is formed coupled to the data bar storage node, and a second capacitor is formed coupled to the data storage node. The first and second capacitors comprise a first conductor layer overlying a second conductor layer with a dielectric layer therebetween. One of the first and second conductor layers is coupled to ground. A new SRAM device is disclosed.
摘要翻译：实现了在集成电路器件中形成SRAM存储单元的新方法。该方法包括提供具有数据存储节点和数据条存储节点的双稳态触发器单元。形成耦合到数据条存储节点的第一电容器，并且形成耦合到数据存储节点的第二电容器。第一和第二电容器包括覆盖在其间具有介电层的第二导体层的第一导体层。第一和第二导体层中的一个耦合到地。公开了一种新的SRAM器件。

138. 发明授权

US07355233B2 Apparatus and method for multiple-gate semiconductor device with angled sidewalls 有权
标题翻译：具有倾斜侧壁的多栅极半导体器件的装置和方法
公开(公告)号：US07355233B2
公开(公告)日：2008-04-08
申请号：US10844197
申请日：2004-05-12
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L29/7853 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/7842 , H01L29/78684
摘要： A multiple-gate transistor has an active region with a side that forms an interior angle with the base of the active region of less than 80°. A process for fabricating a FinFET includes the steps of etching a silicon-on-insulator wafer to form an active region, including the source, channel, and drain, with vertically angled sidewalls.
摘要翻译：多栅极晶体管具有有源区域，其侧面与有源区域的基极形成小于80°的内角。制造FinFET的方法包括以下步骤：蚀刻绝缘体上硅晶片以形成具有垂直成角度侧壁的源极，沟道和漏极的有源区。

139. 发明申请

US20080031045A1 Semiconductor devices with source and bulk coupled to separate voltage supplies 有权
标题翻译：源极和体积耦合到单独的电压源的半导体器件
公开(公告)号：US20080031045A1
公开(公告)日：2008-02-07
申请号：US11498363
申请日：2006-08-02
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： G11C16/04
CPC分类号： G11C5/14 , G11C11/413 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor transistor array is disclosed having a plurality of identical transistors, with sources of the transistors commonly coupled to a first voltage supply, and bulks of the transistors commonly coupled to a second voltage supply which is different from the first voltage supply, wherein different voltages can be supplied to the sources and bulks.
摘要翻译：公开了一种半导体晶体管阵列，其具有多个相同的晶体管，晶体管的源极共同耦合到第一电压源，并且晶体管的大部分共同耦合到与第一电压源不同的第二电压源，其中不同的电压可以提供给源和批量。

140. 发明申请

US20070235765A1 Memory cells and semiconductor memory device using the same 有权
标题翻译：存储单元和半导体存储器件使用相同
公开(公告)号：US20070235765A1
公开(公告)日：2007-10-11
申请号：US11390707
申请日：2006-03-28
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L27/10 , H01L29/73
CPC分类号： H01L27/1104 , H01L27/11
摘要： Memory cells and semiconductor memory devices using the same. A substrate comprises two cross-coupled inverters and first and second pass-gate transistors formed therein, the inverters having a data storage node and a date bar storage node coupled to first terminals of the first and second pass-gate transistors. A first conductive layer is disposed on the substrate and comprises a bit line and a complementary bit line electrically connected to second terminals of the first and second pass-gate transistors respectively. A second conductive layer is disposed on the first conductive layer and comprises two first power lines covering the bit line and the complementary bit line respectively, wherein the first power lines, the bit line and the complementary bit line are parallel.
摘要翻译：存储单元和使用其的半导体存储器件。基板包括两个交叉耦合的反相器和形成在其中的第一和第二通过栅极晶体管，反相器具有耦合到第一和第二通过栅极晶体管的第一端子的数据存储节点和日期条存储节点。第一导电层设置在衬底上，并且包括分别与第一和第二通过栅极晶体管的第二端子电连接的位线和互补位线。第二导电层设置在第一导电层上，并且分别包括覆盖位线和互补位线的两个第一电源线，其中第一电源线，位线和互补位线是平行的。

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