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131. 发明申请

US20110147818A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110147818A1
公开(公告)日：2011-06-23
申请号：US12717499
申请日：2010-03-04
申请人： Ryota KATSUMATA , Yoshiaki Fukuzumi , Masaru Kidoh , Masaru Kito , Hideaki Aochi
发明人： Ryota KATSUMATA , Yoshiaki Fukuzumi , Masaru Kidoh , Masaru Kito , Hideaki Aochi
IPC分类号： H01L27/105
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/792
摘要： A nonvolatile semiconductor memory device includes: a substrate; a memory multilayer body with a plurality of insulating films and electrode films alternately stacked therein, the memory multilayer body being provided on a memory array region of the substrate; a semiconductor pillar buried in the memory multilayer body and extending in stacking direction of the insulating films and the electrode films; a charge storage film provided between one of the electrode films and the semiconductor pillar; a dummy multilayer body with a plurality of the insulating films and the electrode films alternately stacked therein and a dummy hole formed therein, the dummy multilayer body being provided on a peripheral circuit region of the substrate; an insulating member buried in the dummy hole; and a contact buried in the insulating member and extending in the stacking direction.
摘要翻译：非易失性半导体存储器件包括：衬底; 具有交替堆叠的多个绝缘膜和电极膜的存储器多层体，所述存储器多层体设置在所述衬底的存储器阵列区域上; 埋入存储器多层体中并在绝缘膜和电极膜的堆叠方向上延伸的半导体柱; 设置在所述电极膜和所述半导体柱之间的电荷存储膜; 具有多个绝缘膜和电极膜交替堆叠的虚设多层体和形成在其中的虚拟孔，所述虚设多层体设置在所述基板的外围电路区域上; 埋在虚拟孔中的绝缘构件; 以及埋入绝缘构件中并沿堆叠方向延伸的触点。

132. 发明授权

US08378406B2 Multilayer stacked type nonvolatile semiconductor memory device 有权
标题翻译：多层堆叠型非易失性半导体存储器件
公开(公告)号：US08378406B2
公开(公告)日：2013-02-19
申请号：US12717499
申请日：2010-03-04
申请人： Ryota Katsumata , Yoshiaki Fukuzumi , Masaru Kidoh , Masaru Kito , Hideaki Aochi
发明人： Ryota Katsumata , Yoshiaki Fukuzumi , Masaru Kidoh , Masaru Kito , Hideaki Aochi
IPC分类号： H01L29/76
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/792
摘要： A nonvolatile semiconductor memory device includes: a substrate; a memory multilayer body with a plurality of insulating films and electrode films alternately stacked therein, the memory multilayer body being provided on a memory array region of the substrate; a semiconductor pillar buried in the memory multilayer body and extending in stacking direction of the insulating films and the electrode films; a charge storage film provided between one of the electrode films and the semiconductor pillar; a dummy multilayer body with a plurality of the insulating films and the electrode films alternately stacked therein and a dummy hole formed therein, the dummy multilayer body being provided on a peripheral circuit region of the substrate; an insulating member buried in the dummy hole; and a contact buried in the insulating member and extending in the stacking direction.
摘要翻译：非易失性半导体存储器件包括：衬底; 具有交替堆叠的多个绝缘膜和电极膜的存储器多层体，所述存储器多层体设置在所述衬底的存储器阵列区域上; 埋入存储器多层体中并在绝缘膜和电极膜的堆叠方向上延伸的半导体柱; 设置在所述电极膜和所述半导体柱之间的电荷存储膜; 具有多个绝缘膜和电极膜交替堆叠的虚设多层体和形成在其中的虚拟孔，所述虚设多层体设置在所述基板的外围电路区域上; 埋在虚拟孔中的绝缘构件; 以及埋入绝缘构件中并沿堆叠方向延伸的触点。

133. 发明授权

US08334551B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08334551B2
公开(公告)日：2012-12-18
申请号：US13120987
申请日：2009-08-25
申请人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Ryota Katsumata , Masaru Kito , Hideaki Aochi , Akihiro Nitayama
发明人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Ryota Katsumata , Masaru Kito , Hideaki Aochi , Akihiro Nitayama
IPC分类号： H01L29/792 , G11C11/34
CPC分类号： H01L27/1157 , G11C5/02 , G11C16/0483 , G11C16/08 , G11C16/30 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L29/7926
摘要： Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n
摘要翻译：每个存储块包括：在第一区域上平行于衬底扩展的第一导电层，n个第一导电层的层以层叠方向形成并由多个存储器串共享; 第一半导体层; 和电荷蓄积层。对于每个存储块，存储器串按第二方向布置有m列。布线层沿第二方向布置，形成为从存储块的一侧沿第一方向延伸到第一导电层的一端附近，并且经由接触插塞连接到第一导电层。满足式（1）所示的关系：（式1）m> = n

134. 发明授权

US07539056B2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US07539056B2
公开(公告)日：2009-05-26
申请号：US11896261
申请日：2007-08-30
申请人： Ryota Katsumata , Masaru Kito , Hideaki Aochi , Hiroyasu Tanaka , Masaru Kidoh , Mitsuru Sato
发明人： Ryota Katsumata , Masaru Kito , Hideaki Aochi , Hiroyasu Tanaka , Masaru Kidoh , Mitsuru Sato
IPC分类号： G11C16/04
CPC分类号： G11C16/24 , G11C16/0483 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： In a NAND type flash memory, control electrodes of first select transistors in a plurality memory cell units extending along a data line is integrated to constitute a first select signal line while control electrodes of second select transistor are integrated to constitute a second select signal line. The second select signal line is displaced from the first select signal line by a half pitch.
摘要翻译：在NAND型闪速存储器中，集成了沿着数据线延伸的多个存储单元单元中的第一选择晶体管的控制电极，以构成第一选择信号线，同时第二选择晶体管的控制电极被积分以构成第二选择信号线。第二选择信号线从第一选择信号线移位半个间距。

135. 发明授权

US08189391B2 Non-volatile semiconductor storage device including a control circuit 有权
标题翻译：包括控制电路的非易失性半导体存储装置
公开(公告)号：US08189391B2
公开(公告)日：2012-05-29
申请号：US12620986
申请日：2009-11-18
申请人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Masaru Kito , Ryota Katsumata , Hideaki Aochi , Akihiro Nitayama , Takashi Maeda , Tomoo Hishida
发明人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Masaru Kito , Ryota Katsumata , Hideaki Aochi , Akihiro Nitayama , Takashi Maeda , Tomoo Hishida
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/30
摘要： A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.
摘要翻译：非易失性半导体存储装置包括：包括串联连接的多个存储单元的存储串; 第一选择晶体管，其一端连接到存储器串的一端; 第一布线，其一端连接到第一选择晶体管的另一端; 连接到第一选择晶体管的栅极的第二布线。控制电路被配置为在保持第一布线的电压大于第二布线的电压一定电位差的同时，在擦除操作中提高第二布线和第一布线的电压。某些电位差是导致GIDL电流的电位差。

136. 发明申请

US20080149913A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20080149913A1
公开(公告)日：2008-06-26
申请号：US11962862
申请日：2007-12-21
申请人： Hiroyasu TANAKA , Ryota Katsumata , Hideaki Aochi , Masaru Kito , Masaru Kidoh , Mitsuru Sato
发明人： Hiroyasu TANAKA , Ryota Katsumata , Hideaki Aochi , Masaru Kito , Masaru Kidoh , Mitsuru Sato
IPC分类号： H01L27/105 , H01L21/8239 , H01L45/00
CPC分类号： H01L27/2454 , G11C2213/71 , G11C2213/75 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144 , H01L45/146
摘要： A semiconductor memory device is disclosed, which includes a first memory cell array formed on a semiconductor substrate and composed of a plurality of memory cells stacked in layers each having a characteristic change element and a vertical type memory cell transistor connected in parallel to each other, a plurality of second memory cell arrays formed on the semiconductor substrate and having the same structure as the first memory cell array, and arranged in an X direction with respect to the first memory cell array, and a plurality of third memory cell arrays formed on the semiconductor substrate and having the same structure as the first memory cell array, and arranged in a Y direction with respect to the first memory cell array, wherein a gate voltage is applied to gates of the vertical type memory cell transistors of the first to third memory cell arrays in a same layer.
摘要翻译：公开了一种半导体存储器件，其包括形成在半导体衬底上的第一存储器单元阵列，并且由堆叠成各自具有彼此并联连接的特征变化元件和垂直型存储单元晶体管的多个存储单元组成，多个第二存储单元阵列，形成在所述半导体衬底上并具有与所述第一存储单元阵列相同的结构，并且相对于所述第一存储单元阵列沿X方向布置;以及多个第三存储单元阵列，半导体衬底并且具有与第一存储单元阵列相同的结构，并且相对于第一存储单元阵列在Y方向上布置，其中栅极电压被施加到第一至第三存储器的垂直型存储单元晶体管的栅极单元阵列在同一层。

137. 发明申请

US20080067583A1 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20080067583A1
公开(公告)日：2008-03-20
申请号：US11898746
申请日：2007-09-14
申请人： Masaru Kidoh , Ryota Katsumata , Hiroyasu Tanaka , Hideaki Aochi , Masaru Kito
发明人： Masaru Kidoh , Ryota Katsumata , Hiroyasu Tanaka , Hideaki Aochi , Masaru Kito
IPC分类号： H01L29/792 , H01L21/4763
CPC分类号： H01L27/105 , G11C16/0483 , H01L21/8221 , H01L27/0688 , H01L27/115 , H01L27/11529 , H01L27/11556 , H01L27/11568 , H01L27/11582 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile semiconductor memory device includes a substrate, and a plurality of memory strings, the memory string including a first selection transistor including a first pillar shaped semiconductor formed perpendicular to the substrate, a first gate insulating film formed around the first pillar shaped semiconductor, and a first gate electrode formed around the first gate insulating film, and a plurality of memory cells including a second pillar shaped semiconductor formed on the first pillar shaped semiconductor, the diameter of the first pillar shaped semiconductor being larger than the diameter of the second pillar shaped semiconductor at the part where the second pillar shaped semiconductor is connected to the first pillar shaped semiconductor, a first insulating film formed around the second pillar shaped semiconductor, a charge storage layer formed around the first insulating film, a second insulating film formed around the charge storage layer, and first to nth electrodes formed around the second insulating film (n is a natural number not less than 2), the first to nth electrodes being plate shaped, the first to nth electrodes being first to nth conductor layers spread in two dimensions, and a second selection transistor including a third pillar shaped semiconductor formed on the second pillar shaped semiconductor, a second gate insulating film formed around the third pillar shaped semiconductor and a second gate electrode formed around the second gate insulating film.
摘要翻译：非易失性半导体存储器件包括衬底和多个存储器串，所述存储器串包括第一选择晶体管，所述第一选择晶体管包括垂直于所述衬底形成的第一柱状半导体，围绕所述第一柱状半导体形成的第一栅极绝缘膜，以及形成在第一栅极绝缘膜周围的第一栅电极和形成在第一柱状半导体上的包括第二柱状半导体的多个存储单元，第一柱状半导体的直径大于第二柱状半导体的直径在第二柱状半导体与第一柱状半导体连接的部分处的半导体，形成在第二柱状半导体周围的第一绝缘膜，形成在第一绝缘膜周围的电荷存储层，形成在电荷周围的第二绝缘膜存储层和第一至第n电极fo 围绕第二绝缘膜（n是不小于2的自然数），第一至第n电极是板状的，第一至第n电极是第一至第n导体层在二维上扩展，第二选择晶体管包括形成在第二柱状半导体上的第三柱状半导体，围绕第三柱状半导体形成的第二栅极绝缘膜和形成在第二栅极绝缘膜周围的第二栅电极。

138. 发明授权

US08363481B2 Non-volatile semiconductor memory device and method of making the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08363481B2
公开(公告)日：2013-01-29
申请号：US12521997
申请日：2008-01-31
申请人： Masaru Kidoh , Hiroyasu Tanaka , Masaru Kito , Ryota Katsumata , Hideaki Aochi , Mitsuru Sato
发明人： Masaru Kidoh , Hiroyasu Tanaka , Masaru Kito , Ryota Katsumata , Hideaki Aochi , Mitsuru Sato
IPC分类号： G11C16/06
CPC分类号： H01L27/11578 , G11C16/0483 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11568 , H01L27/11575 , H01L27/11582
摘要： A non-volatile semiconductor memory device according to the present invention includes a substrate; a first word-line provided above the substrate surface, the first word-line having a plate shape in an area where a memory cell is formed; a second word-line provided above the first word-line surface, the second word-line having a plate shape; a plurality of metal wirings connecting the first and second word-lines with a driver circuit; and a plurality of contacts connecting the first and second word-lines with the metal wirings. The contact of the first word-line is formed in a first word-line contact area. The contact of the second word-line is formed in a second word-line contact area. The first word-line contact area is provided on a surface of the first word-line that is drawn to the second word-line contact area.
摘要翻译：根据本发明的非易失性半导体存储器件包括：衬底; 设置在所述衬底表面上方的第一字线，所述第一字线在形成存储器单元的区域中具有板形; 设置在所述第一字线表面上方的第二字线，所述第二字线具有板形; 将第一和第二字线与驱动电路连接的多个金属布线; 以及将第一和第二字线与金属布线连接的多个触点。第一字线的接触形成在第一字线接触区域中。第二字线的接触形成在第二字线接触区域中。第一字线接触区域被提供在第一字线的被拉到第二字线接触区域的表面上。

139. 发明申请

US20110175159A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20110175159A1
公开(公告)日：2011-07-21
申请号：US13120987
申请日：2009-08-25
申请人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Ryota Katsumata , Masaru Kito , Hideaki Aochi , Akihiro Nitayama
发明人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Ryota Katsumata , Masaru Kito , Hideaki Aochi , Akihiro Nitayama
IPC分类号： H01L29/792
CPC分类号： H01L27/1157 , G11C5/02 , G11C16/0483 , G11C16/08 , G11C16/30 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L29/7926
摘要： Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n
摘要翻译：每个存储块包括：在第一区域上平行于衬底扩展的第一导电层，n个第一导电层的层以层叠方向形成并由多个存储器串共享; 第一半导体层; 和电荷蓄积层。对于每个存储块，存储器串按第二方向布置有m列。布线层沿第二方向布置，形成为从存储块的一侧沿第一方向延伸到第一导电层的一端附近，并且经由接触插塞连接到第一导电层。满足式（1）所示的关系：（式1）m> = n

140. 发明申请

US20100039865A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MAKING THE SAME 失效
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20100039865A1
公开(公告)日：2010-02-18
申请号：US12521997
申请日：2008-01-31
申请人： Masaru Kidoh , Hiroyasu Tanaka , Masaru Kito , Ryota Katsumata , Hideaki Aochi , Mitsuru Sato
发明人： Masaru Kidoh , Hiroyasu Tanaka , Masaru Kito , Ryota Katsumata , Hideaki Aochi , Mitsuru Sato
IPC分类号： G11C16/06 , H01L29/792 , H01L21/4763
CPC分类号： H01L27/11578 , G11C16/0483 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11568 , H01L27/11575 , H01L27/11582
摘要： A non-volatile semiconductor memory device according to the present invention includes a substrate; a first word-line provided above the substrate surface, the first word-line having a plate shape in an area where a memory cell is formed; a second word-line provided above the first word-line surface, the second word-line having a plate shape; a plurality of metal wirings connecting the first and second word-lines with a driver circuit; and a plurality of contacts connecting the first and second word-lines with the metal wirings. The contact of the first word-line is formed in a first word-line contact area. The contact of the second word-line is formed in a second word-line contact area. The first word-line contact area is provided on a surface of the first word-line that is drawn to the second word-line contact area.
摘要翻译：根据本发明的非易失性半导体存储器件包括：衬底; 设置在所述衬底表面上方的第一字线，所述第一字线在形成存储器单元的区域中具有板形; 设置在所述第一字线表面上方的第二字线，所述第二字线具有板形; 将第一和第二字线与驱动电路连接的多个金属布线; 以及将第一和第二字线与金属布线连接的多个触点。第一字线的接触形成在第一字线接触区域中。第二字线的接触形成在第二字线接触区域中。第一字线接触区域被提供在第一字线的被拉到第二字线接触区域的表面上。

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