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131. 发明申请

US20110220987A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110220987A1
公开(公告)日：2011-09-15
申请号：US12841662
申请日：2010-07-22
申请人： Hiroyasu Tanaka , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Hideaki Aochi
发明人： Hiroyasu Tanaka , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Hideaki Aochi
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11578 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, an interconnection, and a contact plug. The base includes a substrate and a peripheral circuit formed on a surface of the substrate. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base. The memory film is provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers. The memory film includes a charge storage film. The interconnection is provided below the stacked body. The interconnection electrically connects the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region and the peripheral circuit. The contact plug pierces the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region.
摘要翻译：根据一个实施例，半导体存储器件包括基底，堆叠体，存储膜，通道体，互连和接触插塞。基底包括形成在基片的表面上的基片和外围电路。堆叠体包括多个导电层和交替堆叠在基底之上的多个绝缘层。记忆膜设置在通过层叠体冲压的存储孔的内壁上，以到达导电层的最下层。记忆膜包括电荷存储膜。互连设置在堆叠体的下方。互连电连接布置在存储单元阵列区域的外部的互连区域中的导电层的最下层和外围电路。接触插塞刺穿互连区域中的层叠体到达互连区域中的导电层的最下层。

132. 发明申请

US20080315296A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20080315296A1
公开(公告)日：2008-12-25
申请号：US12142289
申请日：2008-06-19
申请人： Hiroyasu TANAKA , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kido , Hideaki Aochi , Mitsuru Sato , Yasuyuki Matsuoka
发明人： Hiroyasu TANAKA , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kido , Hideaki Aochi , Mitsuru Sato , Yasuyuki Matsuoka
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/115 , H01L27/11556
摘要： A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.
摘要翻译：非易失性半导体存储装置10具有多个串联连接的多个电可重写存储晶体管MTr1-MTr4的存储器串100。存储器串100包括沿垂直于衬底的方向延伸的柱状半导体CLmn，经由绝缘膜形成在柱状半导体CLmn周围的多个电荷累积层，以及与柱状半导体接触的漏极侧SGD上的选择栅极线，以配置晶体管。漏极侧SGD上的选择栅极线在漏极侧SGDd上具有较低的选择栅极线，每个栅极配置有一定间距的间隔，漏极侧SGDu上的选择栅极线位于高于漏极侧SGDd上的下部选择栅极线设置在漏极侧SGDd的下部选择栅极线之间的间隙。

133. 发明授权

US08335111B2 Non-volatile semiconductor storage device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储装置及其制造方法
公开(公告)号：US08335111B2
公开(公告)日：2012-12-18
申请号：US12886854
申请日：2010-09-21
申请人： Yoshiaki Fukuzumi , Ryota Katsumata , Megumi Ishiduki , Hideaki Aochi
发明人： Yoshiaki Fukuzumi , Ryota Katsumata , Megumi Ishiduki , Hideaki Aochi
IPC分类号： G11C16/04 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11578 , G11C16/0483 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： A non-volatile semiconductor storage device includes: a memory string; a select transistor; and a carrier selection element. The select transistor has one end connected to one end of the memory string. The carrier selection element has one end connected to the other end of the select transistor, and selects a majority carrier flowing through respective bodies of the memory transistors and the select transistor. The carrier selection element includes: a third semiconductor layer; a metal layer; a second gate insulation layer; and a third conductive layer. The metal layer extends in the vertical direction. The metal layer extends in the vertical direction from the top of the third semiconductor layer. The second gate insulation layer surrounds the third semiconductor layer and the metal layer. The third conductive layer surrounds the third semiconductor layer and the metal layer via the second gate insulation layer and extends in a parallel direction.
摘要翻译：非易失性半导体存储装置包括：存储器串; 选择晶体管; 和载波选择元件。选择晶体管的一端连接到存储器串的一端。载波选择元件的一端连接到选择晶体管的另一端，并且选择流过存储晶体管和选择晶体管的相应体的多数载流子。载体选择元件包括：第三半导体层; 金属层; 第二栅绝缘层; 和第三导电层。金属层沿垂直方向延伸。金属层从第三半导体层的顶部沿垂直方向延伸。第二栅极绝缘层包围第三半导体层和金属层。第三导电层经由第二栅极绝缘层围绕第三半导体层和金属层，并沿平行方向延伸。

134. 发明授权

US09064975B2 Shift register memory and method of manufacturing the same 有权
标题翻译：移位寄存器及其制造方法
公开(公告)号：US09064975B2
公开(公告)日：2015-06-23
申请号：US13409652
申请日：2012-03-01
申请人： Yoshiaki Fukuzumi , Masaru Kito , Tomoko Fujiwara , Kaori Kawasaki , Hideaki Aochi
发明人： Yoshiaki Fukuzumi , Masaru Kito , Tomoko Fujiwara , Kaori Kawasaki , Hideaki Aochi
IPC分类号： H01L29/765 , H01L21/84 , H01L27/10 , H01L27/115 , H01L27/12 , G11C19/00
CPC分类号： H01L21/84 , G11C19/00 , H01L27/10 , H01L27/11517 , H01L27/1203
摘要： In one embodiment, a shift register memory includes first and second control electrodes extending in a first direction parallel to a surface of a substrate, and facing each other in a second direction perpendicular to the first direction. The memory further includes a plurality of first floating electrodes provided in a line on a first control electrode side between the first and second control electrodes. The memory further includes a plurality of second floating electrodes provided in a line on a second control electrode side between the first and second control electrodes. Each of the first and second floating electrodes has a planar shape which is mirror-asymmetric with respect to a plane perpendicular to the first direction.
摘要翻译：在一个实施例中，移位寄存器存储器包括在平行于衬底表面的第一方向上延伸的第一和第二控制电极，并且在垂直于第一方向的第二方向上彼此面对。存储器还包括设置在第一和第二控制电极之间的第一控制电极侧的一行中的多个第一浮置电极。存储器还包括设置在第一和第二控制电极之间的第二控制电极侧的一行中的多个第二浮置电极。第一和第二浮动电极中的每一个具有相对于垂直于第一方向的平面镜像不对称的平面形状。

135. 发明申请

US20120195128A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME 审中-公开
标题翻译：非易失性半导体存储器件及其驱动方法
公开(公告)号：US20120195128A1
公开(公告)日：2012-08-02
申请号：US13177719
申请日：2011-07-07
申请人： Tomoko FUJIWARA , Masaru Kito , Yoshiaki Fukuzumi , Hideaki Aochi
发明人： Tomoko FUJIWARA , Masaru Kito , Yoshiaki Fukuzumi , Hideaki Aochi
IPC分类号： G11C16/10
CPC分类号： H01L27/11573 , G11C11/5628 , G11C16/0483 , G11C16/10 , H01L27/11582 , H01L29/792
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a multilayer structure, a semiconductor pillar, a storage layer, an inner insulating film, an outer insulating film, a memory cell transistor. The control unit performs control of setting the thresholds of the memory transistor to either positive or negative, and performs control so that, with one of the thresholds most distant from 0 volts being defined as n-th threshold, width of distribution of m-th threshold (m being an integer of 1 or more smaller than n) having a sign being same as the n-th threshold is set narrower than width of distribution of the n-th threshold.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括存储器单元和控制单元。存储单元包括多层结构，半导体柱，存储层，内绝缘膜，外绝缘膜，存储单元晶体管。控制单元执行将存储晶体管的阈值设置为正或负的控制，并进行控制，使得在距离最远的0V的阈值中的一个被定义为第n阈值时，第m行的分布宽度具有与第n个阈值相同的符号的阈值（m为小于n的1以上的整数）被设定为窄于第n阈值的分布宽度。

136. 发明授权

US07982260B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07982260B2
公开(公告)日：2011-07-19
申请号：US12013672
申请日：2008-01-14
申请人： Yoshiaki Fukuzumi , Hideaki Aochi , Ryota Katsumata
发明人： Yoshiaki Fukuzumi , Hideaki Aochi , Ryota Katsumata
IPC分类号： H01L27/115 , H01L29/792
CPC分类号： H01L27/115 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11556 , H01L27/11582 , H01L29/42324 , H01L29/4234 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： The semiconductor device includes a substrate having a conductive layer formed on its surface. The conductive layer has a columnar semiconductor formed thereon. The columnar semiconductor has an insulating layer formed therearound. The insulating layer has an electrode film formed therearound. The electrode film functions as an gate electrode of a transistor. The electrode film includes an laminate of two or more conductive films having different work functions.
摘要翻译：半导体器件包括在其表面上形成有导电层的衬底。导电层在其上形成有柱状半导体。柱状半导体具有形成在其周围的绝缘层。绝缘层具有形成在其周围的电极膜。电极膜用作晶体管的栅电极。电极膜包括具有不同功函数的两个或多个导电膜的叠层。

137. 发明申请

US20080173933A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20080173933A1
公开(公告)日：2008-07-24
申请号：US12013672
申请日：2008-01-14
申请人： Yoshiaki Fukuzumi , Hideaki Aochi , Ryota Katsumata
发明人： Yoshiaki Fukuzumi , Hideaki Aochi , Ryota Katsumata
IPC分类号： H01L27/115 , H01L29/792
CPC分类号： H01L27/115 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11556 , H01L27/11582 , H01L29/42324 , H01L29/4234 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： The semiconductor device includes a substrate having a conductive layer formed on its surface. The conductive layer has a columnar semiconductor formed thereon. The columnar semiconductor has an insulating layer formed therearound. The insulating layer has an electrode film formed therearound. The electrode film functions as an gate electrode of a transistor. The electrode film includes an laminate of two or more conductive films having different work functions.
摘要翻译：半导体器件包括在其表面上形成有导电层的衬底。导电层在其上形成有柱状半导体。柱状半导体具有形成在其周围的绝缘层。绝缘层具有形成在其周围的电极膜。电极膜用作晶体管的栅电极。电极膜包括具有不同功函数的两个或多个导电膜的叠层。

138. 发明授权

US08476708B2 Semiconductor memory device having a circuit formed on a single crystal semiconductor layer with varied germanium concentration 有权
标题翻译：具有形成在具有不同锗浓度的单晶半导体层上的电路的半导体存储器件
公开(公告)号：US08476708B2
公开(公告)日：2013-07-02
申请号：US13346888
申请日：2012-01-10
申请人： Yoshiaki Fukuzumi , Hideaki Aochi , Masaru Kito , Kiyotaka Miyano , Shinji Mori , Ichiro Mizushima
发明人： Yoshiaki Fukuzumi , Hideaki Aochi , Masaru Kito , Kiyotaka Miyano , Shinji Mori , Ichiro Mizushima
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/792
CPC分类号： H01L27/11582 , H01L27/0688 , H01L27/11573 , H01L27/11578 , H01L27/1207
摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion.The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.
摘要翻译：根据一个实施例，半导体存储器件包括半导体衬底，存储单元阵列部分，单晶半导体层和电路部分。存储单元阵列部分形成在半导体衬底上，并且包括存储单元。半导体层形成在存储单元阵列部分上，并且通过形成在延伸穿过存储单元阵列部分的孔中而连接到半导体衬底。电路部分形成在半导体层上。半导体层的下部的Ge浓度高于半导体层的上部的Ge浓度。

139. 发明申请

US20120181602A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120181602A1
公开(公告)日：2012-07-19
申请号：US13346888
申请日：2012-01-10
申请人： Yoshiaki Fukuzumi , Hideaki Aochi , Masaru Kito , Kiyotaka Miyano , Shinji Mori , Ichiro Mizushima
发明人： Yoshiaki Fukuzumi , Hideaki Aochi , Masaru Kito , Kiyotaka Miyano , Shinji Mori , Ichiro Mizushima
IPC分类号： H01L27/105 , H01L21/8239
CPC分类号： H01L27/11582 , H01L27/0688 , H01L27/11573 , H01L27/11578 , H01L27/1207
摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion.The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.
摘要翻译：根据一个实施例，半导体存储器件包括半导体衬底，存储单元阵列部分，单晶半导体层和电路部分。存储单元阵列部分形成在半导体衬底上，并且包括存储单元。半导体层形成在存储单元阵列部分上，并且通过形成在延伸穿过存储单元阵列部分的孔中而连接到半导体衬底。电路部分形成在半导体层上。半导体层的下部的Ge浓度高于半导体层的上部的Ge浓度。

140. 发明授权

US08643081B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08643081B2
公开(公告)日：2014-02-04
申请号：US13603797
申请日：2012-09-05
申请人： Tomoko Fujiwara , Yoshiaki Fukuzumi , Hideaki Aochi
发明人： Tomoko Fujiwara , Yoshiaki Fukuzumi , Hideaki Aochi
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device comprises a first layer, a first conductive layer, a insulating layer, and a second conductive layer stacked on a substrate, a block insulating layer on inner surfaces of a pair of through-holes formed in the first conductive layer, the insulating layer, and the second conductive layer, and on an inner surface of a connecting hole connecting lower ends of the pair of through-holes, a charge storage layer on the block insulating layer, a second layer on the charge storage layer, and a semiconductor layer on the second layer. The second layer includes an air gap layer on the charge storage layer in the pair of through-holes, and a third conductive layer on the charge storage layer in the connecting hole.
摘要翻译：根据一个实施例，半导体存储器件包括第一层，第一导电层，绝缘层和堆叠在衬底上的第二导电层，在形成在衬底中的一对通孔的内表面上的块绝缘层第一导电层，绝缘层和第二导电层，以及连接在一对通孔的下端的连接孔的内表面上，在块绝缘层上的电荷存储层，电荷上的第二层存储层和第二层上的半导体层。第二层包括一对通孔中的电荷存储层上的气隙层和连接孔中的电荷存储层上的第三导电层。

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