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131. 发明授权

US07522457B2 Systems for erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage 有权
标题翻译：用于在非易失性存储器中擦除电压操作的系统用于阈值电压的受控偏移
公开(公告)号：US07522457B2
公开(公告)日：2009-04-21
申请号：US11773927
申请日：2007-07-05
申请人： Gerrit Jan Hemink , Teruhiko Kamei
发明人： Gerrit Jan Hemink , Teruhiko Kamei
IPC分类号： G11C11/34
CPC分类号： G11C16/344 , G11C11/5635 , G11C16/0483 , G11C16/16 , G11C16/3404 , G11C16/3445 , G11C2211/5621
摘要： The erase voltage applied to a set of non-volatile storage elements being erased is structured to provide controlled shifts in the threshold voltage of the storage elements. The erase voltage is applied as a series of voltage pulses, when necessary, to shift the threshold voltage of to-be-erased memory cells below a verify level indicative of an erased condition. To avoid over-erasing the memory cells, the second erase voltage pulse is decreased, or not increased, in magnitude when compared to the previously applied voltage pulse. By decreasing or not increasing the size of the erase voltage, the amount of charge transferred from the cells by the second pulse is controlled to more accurately position an erased threshold voltage distribution for the cells near the verify level. Subsequent erase voltage pulses are increased in magnitude to provide further erasing when needed.
摘要翻译：施加到被擦除的一组非易失性存储元件的擦除电压被构造成提供存储元件的阈值电压的受控偏移。当需要时，将擦除电压作为一系列电压脉冲施加以将被擦除的存储器单元的阈值电压移动到指示擦除状态的验证电平以下。为了避免过度擦除存储单元，与先前施加的电压脉冲相比，第二擦除电压脉冲的幅度减小或不增加。通过减小或不增加擦除电压的大小，控制从单元传输的第二脉冲的电荷量，以更准确地定位靠近验证电平的单元的擦除的阈值电压分布。随后的擦除电压脉冲的幅度增大，以便在需要时进一步擦除。

132. 发明申请

US20090073761A1 Self-Boosting System for Flash Memory Cells 有权
标题翻译：闪存单元的自升压系统
公开(公告)号：US20090073761A1
公开(公告)日：2009-03-19
申请号：US12276186
申请日：2008-11-21
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/10 , G11C16/0483
摘要： A low voltage of the order of or one to three volts instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a NAND flash device to reduce or prevent the shifting of threshold voltage of the memory cells coupled to word line zero during the programming cycles of the different cells of the NAND strings. This may be implemented in any one of a variety of different self boosting schemes including erased areas self boosting and local self boosting schemes. In a modified erased area self boosting scheme, low voltages are applied to two or more word lines on the source side of the selected word line to reduce band-to-band tunneling and to improve the isolation between two boosted channel regions. In a modified local self boosting scheme, zero volt or low voltages are applied to two or more word lines on the source side and to two or more word lines on the drain side of the selected word line to reduce band-to-band tunneling and to improve the isolation of the channel areas coupled to the selected word line.
摘要翻译：代替中间VPASS电压（例如5至10伏的数量级）的一级或一到三伏的低电压被施加到紧邻NAND闪存器件的源极或漏极侧选择栅极的字线零点以减少或防止在NAND串的不同单元的编程周期期间耦合到字线零的存储单元的阈值电压偏移。这可以在各种不同的自增强方案中的任何一种中实现，包括擦除区域自增强和局部自增强方案。在修改的擦除区域自增强方案中，将低电压施加到所选字线的源极侧上的两个或更多个字线，以减少带间隧穿并改善两个增强的通道区域之间的隔离。在修改后的局部自增强方案中，将零电压或低电压施加到源极侧的两条或更多条字线和所选择的字线的漏极侧上的两条或多条字线，以减少带间隧穿和以改善耦合到所选字线的通道区域的隔离。

133. 发明授权

US07471566B2 Self-boosting system for flash memory cells 有权
标题翻译：闪存单元的自增强系统
公开(公告)号：US07471566B2
公开(公告)日：2008-12-30
申请号：US11609688
申请日：2006-12-12
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483
摘要： A low voltage of the order of or one to three volts instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a NAND flash device to reduce or prevent the shifting of threshold voltage of the memory cells coupled to word line zero during the programming cycles of the different cells of the NAND strings. This may be implemented in any one of a variety of different self boosting schemes including erased areas self boosting and local self boosting schemes. In a modified erased area self boosting scheme, low voltages are applied to two or more word lines on the source side of the selected word line to reduce band-to-band tunneling and to improve the isolation between two boosted channel regions. In a modified local self boosting scheme, zero volt or low voltages are applied to two or more word lines on the source side and to two or more word lines on the drain side of the selected word line to reduce band-to-band tunneling and to improve the isolation of the channel areas coupled to the selected word line.
摘要翻译：代替中间VPASS电压（例如5至10伏的数量级）的一级或一到三伏的低电压被施加到紧邻NAND闪存器件的源极或漏极侧选择栅极的字线零点以减少或防止在NAND串的不同单元的编程周期期间耦合到字线零的存储单元的阈值电压偏移。这可以在各种不同的自增强方案中的任何一种中实现，包括擦除区域自增强和局部自增强方案。在修改的擦除区域自增强方案中，将低电压施加到所选字线的源极侧上的两个或更多个字线，以减少带间隧穿并改善两个增强的通道区域之间的隔离。在修改后的局部自增强方案中，将零电压或低电压施加到源极侧的两条或更多条字线和所选择的字线的漏极侧上的两条或多条字线，以减少带间隧穿和以改善耦合到所选字线的通道区域的隔离。

134. 发明申请

US20080316829A1 SYSTEM FOR VERIFYING NON-VOLATILE STORAGE USING DIFFERENT VOLTAGES 有权
标题翻译：使用不同电压验证非易失性存储的系统
公开(公告)号：US20080316829A1
公开(公告)日：2008-12-25
申请号：US12203544
申请日：2008-09-03
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/3418 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： When performing a data sensing operation, including a verify operation during programming of non-volatile storage elements (or, in some cases, during a read operation after programming), a first voltage is used for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. In some embodiments, the second voltage is lower than the first voltage.
摘要翻译：当执行数据检测操作时，包括在编程非易失性存储元件期间（或在某些情况下，在编程之后的读取操作期间）中的验证操作，第一电压被用于已经经过编程的未被选择的字线对未经过编程操作的未选字线使用第二电压。在一些实施例中，第二电压低于第一电压。

135. 发明授权

US07433241B2 Programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data 有权
标题翻译：通过消除对字线数据的预充电依赖来编程非易失性存储器，减少程序干扰
公开(公告)号：US07433241B2
公开(公告)日：2008-10-07
申请号：US11618580
申请日：2006-12-29
申请人： Yingda Dong , Jeffrey W. Lutze , Dana Lee , Gerrit Jan Hemink
发明人： Yingda Dong , Jeffrey W. Lutze , Dana Lee , Gerrit Jan Hemink
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C7/1048 , G11C11/5628 , G11C16/3418 , G11C16/3427
摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at higher voltages for certain memory cells that may have undergone partial programming.
摘要翻译：在编程期间，未选择的非易失性存储元件组被提升以减少或消除连接到所选字线的目标但未选择的存储器单元的程序干扰。在将程序电压施加到所选择的字线并升高未选择的组之前，未选择的组被预先充电，以通过为未选择的组提供更大的增强电位来进一步减少或消除程序干扰。在预充电期间，对于可能已经经过部分编程的某些存储器单元，在较高电压下提供一个或多个预充电使能信号。

136. 发明申请

US20080117684A1 SYSTEMS FOR CONTROLLED BOOSTING IN NON-VOLATILE MEMORY SOFT PROGRAMMING 有权
标题翻译：用于在非易失性存储器软件编程中进行控制的系统
公开(公告)号：US20080117684A1
公开(公告)日：2008-05-22
申请号：US11560751
申请日：2006-11-16
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3404
摘要： A soft programming pre-charge voltage provides boosting control during soft programming operations for non-volatile memory devices. A pre-charge voltage can be applied to the word lines of a block of memory cells to enable pre-charging of the channel region of a NAND string to be inhibited from soft programming. The level of boosting in the channel region of the inhibited NAND string is governed by the pre-charge voltage and the soft programming voltage. By controlling the pre-charge voltage, more reliable and consistent channel boosting can be achieved. In one embodiment, the pre-charge voltage is increased between applications of the soft programming voltage to reduce or eliminate a rise in the channel's boosted potential. In one embodiment, the soft programming pre-charge voltage level(s) is determined during testing that is performed as part of a manufacturing process.
摘要翻译：软编程预充电电压在非易失性存储器件的软编程操作期间提供升压控制。可以将预充电电压施加到一块存储器单元的字线，以使得能够预先对NAND串的通道区进行预编程以禁止软编程。被禁止的NAND串的通道区域中的升压电平由预充电电压和软编程电压控制。通过控制预充电电压，可以实现更可靠和一致的通道增压。在一个实施例中，在应用软编程电压之间增加预充电电压以减少或消除通道的升压电位的上升。在一个实施例中，软编程预充电电压电平在作为制造过程的一部分执行的测试期间被确定。

137. 发明申请

US20080101126A1 FASTER PROGRAMMING OF HIGHEST MULTI-LEVEL STATE FOR NON-VOLATILE MEMORY 有权
标题翻译：更快地编写非易失性存储器的最高级别状态
公开(公告)号：US20080101126A1
公开(公告)日：2008-05-01
申请号：US11554223
申请日：2006-10-30
申请人： Gerrit Jan Hemink , Shih-Chung Lee
发明人： Gerrit Jan Hemink , Shih-Chung Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： A coarse/fine programming technique is used for programming to lower states while using a standard technique (not coarse/fine programming) for programming to the highest state(s). However, when the programming of the lower states is finished, a number of programming pulses are still needed to program the highest state. To improve the programming speed, a bigger step size and longer programming pulse can be used from the moment that the lowest states have been programmed. At the same time, the programming technique for the highest state can be changed to a coarse/fine programming technique.
摘要翻译：在使用标准技术（不是粗/精编程）来编程到最高状态时，粗/精编程技术用于编程以降低状态。然而，当下部状态的编程完成时，仍然需要多个编程脉冲来编程最高状态。为了提高编程速度，从最低状态被编程的时刻起，可以使用更大的步长和更长的编程脉冲。同时，用于最高状态的编程技术可以改变为粗/精编程技术。

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