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131. 发明授权

US08937357B2 One-time programmable semiconductor device 有权
标题翻译：一次性可编程半导体器件
公开(公告)号：US08937357B2
公开(公告)日：2015-01-20
申请号：US12660603
申请日：2010-03-01
申请人： Frank Hui , Xiangdong Chen
发明人： Frank Hui , Xiangdong Chen
IPC分类号： H01L27/112
CPC分类号： H01L27/112 , H01L27/11206
摘要： According to one embodiment, a one-time programmable (OTP) semiconductor device includes a programming dielectric under a patterned electrode and over an implant region, where the programming dielectric forms a programming region of the OTP semiconductor device. The OTP semiconductor device further includes an isolation region laterally separating the programming dielectric from a coupled semiconductor structure, where the isolation region can be used in conjunction with the patterned electrode and the implant region to protect the coupled semiconductor structure. In one embodiment, the programming dielectric comprises a gate dielectric. In another embodiment, the electrode and implant regions are doped to be electrochemically similar.
摘要翻译：根据一个实施例，一次性可编程（OTP）半导体器件包括在图案化电极下面和注入区域上的编程电介质，其中编程电介质形成OTP半导体器件的编程区域。 OTP半导体器件还包括将编程电介质横向分离成耦合的半导体结构的隔离区，其中隔离区域可与图案化电极和注入区域一起使用以保护耦合的半导体结构。在一个实施例中，编程电介质包括栅极电介质。在另一个实施例中，电极和注入区被掺杂以在电化学上相似。

132. 发明授权

US08847224B2 Fin-based bipolar junction transistor and method for fabrication 有权
标题翻译：鳍式双极结型晶体管及其制造方法
公开(公告)号：US08847224B2
公开(公告)日：2014-09-30
申请号：US13246710
申请日：2011-09-27
申请人： Wei Xia , Xiangdong Chen
发明人： Wei Xia , Xiangdong Chen
IPC分类号： H01L29/10 , H01L29/732 , H01L29/66
CPC分类号： H01L29/66272 , H01L29/1004 , H01L29/732
摘要： According to one exemplary embodiment, a fin-based bipolar junction transistor (BJT) includes a wide collector situated in a semiconductor substrate. A fin base is disposed over the wide collector. Further, a fin emitter and an epi emitter are disposed over the fin base. A narrow base-emitter junction of the fin-based BJT is formed by the fin base and the fin emitter and the epi emitter provides increased current conduction and reduced resistance for the fin-based BJT. The epi emitter can be epitaxially formed on the fin emitter and can comprise polysilicon. Furthermore, the fin base and the fin emitter can each comprise single crystal silicon.
摘要翻译：根据一个示例性实施例，鳍式双极结型晶体管（BJT）包括位于半导体衬底中的宽集电极。翅片底座设置在宽收集器上。此外，翅片发射极和外延发射极设置在翅片基底之上。翅片基BJT的窄基极 - 发射极结由翅片基极和鳍发射极形成，并且epi发射极为鳍状BJT提供增加的电流传导和降低的电阻。外延发射体可以外延形成在鳍发射极上并且可以包括多晶硅。此外，散热片基板和散热片发射极可以各自包括单晶硅。

133. 发明授权

US08610221B2 Low mismatch semiconductor device and method for fabricating same 有权
标题翻译：低失配半导体器件及其制造方法
公开(公告)号：US08610221B2
公开(公告)日：2013-12-17
申请号：US12657909
申请日：2010-01-29
申请人： Xiangdong Chen , Akira Ito
发明人： Xiangdong Chen , Akira Ito
IPC分类号： H01L27/088
CPC分类号： H01L21/28 , H01L27/092 , H01L29/78
摘要： Disclosed is a low mismatch semiconductor device that comprises a lightly doped channel region having a first conductivity type and a first dopant concentration in a semiconductor body, and a high-k metal gate stack including a gate metal layer formed over a high-k gate dielectric without having a dielectric cap on the high-k dielectric. The high-k metal gate stack being formed over the lightly doped channel region. The lightly doped channel region may be a P- or N-conductivity region, for example, and may be part of a corresponding P- or N-semiconductor substrate, or a P- or N-well formed in a substrate of the respectively opposite conductivity type. The disclosed semiconductor device, which may be an NMOS or PMOS analog device, for example, can be fabricated as part of an integrated circuit including one or more CMOS logic devices.
摘要翻译：公开了一种低失配半导体器件，其包括在半导体本体中具有第一导电类型和第一掺杂剂浓度的轻掺杂沟道区，以及包括形成在高k栅极电介质上的栅极金属层的高k金属栅堆叠在高k电介质上没有电介质盖。高k金属栅堆叠形成在轻掺杂沟道区上。轻掺杂沟道区可以是例如P型或N-导电性区，并且可以是相应的P-或N-半导体衬底的一部分，也可以是在相对的相对的衬底中形成的P-阱或N阱导电类型。所公开的半导体器件（其可以是例如NMOS或PMOS模拟器件）可以被制造为包括一个或多个CMOS逻辑器件的集成电路的一部分。

134. 发明授权

US08570811B2 FinFET based one-time programmable device and related method 有权
标题翻译：基于FinFET的一次性可编程器件及相关方法
公开(公告)号：US08570811B2
公开(公告)日：2013-10-29
申请号：US13219414
申请日：2011-08-26
申请人： Wei Xia , Xiangdong Chen
发明人： Wei Xia , Xiangdong Chen
IPC分类号： G11C11/34
CPC分类号： H01L29/7855 , G11C11/34 , G11C17/12 , H01L23/5252 , H01L27/11206 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a one-time programmable (OTP) device comprises a memory FinFET in parallel with a sensing FinFET. The memory FinFET and the sensing FinFET share a common source region, a common drain region, and a common channel region. The memory FinFET is programmed by having a ruptured gate dielectric, resulting in the sensing FinFET having an altered threshold voltage and an altered drain current. A method for utilizing such an OTP device comprises applying a programming voltage for rupturing the gate dielectric of the memory FinFET thereby achieving a programmed state of the memory FinFET, and detecting by the sensing FinFET the altered threshold voltage and the altered drain current due to the programmed state of the memory FinFET.
摘要翻译：根据一个实施例，一次性可编程（OTP）器件包括与感测FinFET并联的存储器FinFET。存储器FinFET和感测FinFET共享共源极区，公共漏极区和公共沟道区。存储器FinFET通过具有破裂的栅极电介质来编程，导致感测FinFET具有改变的阈值电压和改变的漏极电流。一种利用这种OTP器件的方法包括施加用于破坏存储器FinFET的栅极电介质的编程电压，从而实现存储器FinFET的编程状态，并且通过感测FinFET检测改变的阈值电压和改变的漏极电流，由于存储器FinFET的编程状态。

135. 发明申请

US20130221499A1 Semiconductor Package with Integrated Electromagnetic Shielding 有权
标题翻译：具有集成电磁屏蔽的半导体封装
公开(公告)号：US20130221499A1
公开(公告)日：2013-08-29
申请号：US13405721
申请日：2012-02-27
申请人： Sampath K.V. Karikalan , Kevin Kunzhong Hu , Sam Ziqun Zhao , Rezaur Rahman Khan , Pieter Vorenkamp , Xiangdong Chen
发明人： Sampath K.V. Karikalan , Kevin Kunzhong Hu , Sam Ziqun Zhao , Rezaur Rahman Khan , Pieter Vorenkamp , Xiangdong Chen
IPC分类号： H01L23/552
CPC分类号： H01L25/0657 , H01L23/147 , H01L23/481 , H01L23/50 , H01L23/5286 , H01L23/552 , H01L2224/02372 , H01L2224/0401 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06537 , H01L2225/06541 , H01L2225/06565 , H01L2924/15311 , H01L2924/15321 , H01L2924/19107 , H01L2924/3025
摘要： There are disclosed herein various implementations of a shield interposer situated between a top active die and a bottom active die for shielding the active dies from electromagnetic noise. One implementation includes an interposer dielectric layer, a through-silicon via (TSV) within the interposer dielectric layer, and an electromagnetic shield. The TSV connects the electromagnetic shield to a first fixed potential. The electromagnetic shield may include a grid of conductive layers laterally extending across the shield interposer. The shield interposer may also include another electromagnetic shield connected to another fixed potential.
摘要翻译：这里公开了位于顶部有源管芯和底部有源管芯之间的屏蔽插入器的各种实现方式，用于屏蔽活动管芯免受电磁噪声。一种实现方式包括内插器电介质层，内插电介质层内的穿硅通孔（TSV）和电磁屏蔽。 TSV将电磁屏蔽连接到第一固定电位。电磁屏蔽可以包括横跨屏蔽插入件横向延伸的导电层格。屏蔽插入器还可以包括连接到另一个固定电位的另一个电磁屏蔽。

136. 发明授权

US08502320B2 Zener diode structure and process 有权
公开(公告)号：US08502320B2
公开(公告)日：2013-08-06
申请号：US13250563
申请日：2011-09-30
申请人： Wei Xia , Xiangdong Chen
发明人： Wei Xia , Xiangdong Chen
IPC分类号： H01L21/70
CPC分类号： H01L21/823814 , H01L21/823807 , H01L24/13 , H01L24/14 , H01L27/0629 , H01L2224/13147 , H01L2224/14104 , H01L2924/12035 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
摘要： A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non-junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

137. 发明授权

US08497564B2 Method for fabricating a decoupling composite capacitor in a wafer and related structure 有权
标题翻译：在晶片中制造去耦复合电容器的方法及相关结构
公开(公告)号：US08497564B2
公开(公告)日：2013-07-30
申请号：US12583016
申请日：2009-08-13
申请人： Xiangdong Chen , Wei Xia
发明人： Xiangdong Chen , Wei Xia
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/40 , H01L28/90 , H01L29/94 , H01L29/945
摘要： According to an exemplary embodiment, a method for fabricating a decoupling composite capacitor in a wafer that includes a dielectric region overlying a substrate includes forming a through-wafer via in the dielectric region and the substrate. The through-wafer via includes a through-wafer via insulator covering a sidewall and a bottom of a through-wafer via opening and a through-wafer via conductor covering the through-wafer via insulator. The method further includes thinning the substrate, forming a substrate backside insulator, forming an opening in the substrate backside insulator to expose the through-wafer via conductor, and forming a backside conductor on the through-wafer via conductor, such that the substrate backside conductor extends over the substrate backside insulator, thereby forming the decoupling composite capacitor. The substrate forms a first decoupling composite capacitor electrode and the through-wafer via conductor and substrate backside conductor form a second decoupling composite capacitor electrode.
摘要翻译：根据示例性实施例，在晶片中制造去耦复合电容器的方法包括覆盖在衬底上的电介质区域包括在电介质区域和衬底中形成贯通晶片通孔。贯通晶片通孔包括覆盖贯通晶片通孔开口的侧壁和底部的贯通晶片通孔绝缘体，以及通过绝缘体覆盖贯通晶片的贯通晶片通孔导体。该方法还包括使衬底变薄，形成衬底背面绝缘体，在衬底背面绝缘体中形成开口以通过导体暴露通过晶片，以及通过导体在透晶片上形成背面导体，使得衬底背侧导体延伸到衬底背面绝缘体上，从而形成去耦复合电容器。衬底形成第一去耦合复合电容器电极，并且通过晶片通孔导体和衬底背侧导体形成第二去耦复合电容器电极。

138. 发明申请

US20130154106A1 Stacked Packaging Using Reconstituted Wafers 审中-公开
标题翻译：使用重构晶片的堆叠包装
公开(公告)号：US20130154106A1
公开(公告)日：2013-06-20
申请号：US13325951
申请日：2011-12-14
申请人： Kevin Kunzhong Hu , Sam Ziqun Zhao , Rezaur Rahman Khan , Pieter Vorenkamp , Sampath K.V. Karikalan , Xiangdong Chen
发明人： Kevin Kunzhong Hu , Sam Ziqun Zhao , Rezaur Rahman Khan , Pieter Vorenkamp , Sampath K.V. Karikalan , Xiangdong Chen
IPC分类号： H01L23/498 , H01L21/78
CPC分类号： H01L25/105 , H01L21/50 , H01L21/78 , H01L23/481 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/24 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/96 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/05572 , H01L2224/12105 , H01L2224/131 , H01L2224/16145 , H01L2224/24011 , H01L2224/24146 , H01L2224/2919 , H01L2224/82039 , H01L2224/82047 , H01L2224/821 , H01L2224/83 , H01L2224/9202 , H01L2224/92133 , H01L2224/92144 , H01L2224/92244 , H01L2224/96 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06548 , H01L2225/1041 , H01L2924/00014 , H01L2924/12042 , H01L2924/15747 , H01L2924/181 , H01L2224/82 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement.
摘要翻译：本公开的示例性实施方案包括具有来自位于底部重构晶片的底模上方的顶部重构晶片的顶模的堆叠封装。顶部模具和底部模具通过绝缘装置彼此绝缘。顶模和底模也通过绝缘装置互连。绝缘装置可以包括在顶模侧面的顶部模塑料和位于底模侧面的底部模塑料。顶部模具和底部模具可以通过至少顶部模塑料相互连接。此外，顶模和底模可以通过在绝缘装置内延伸的导电通孔相互连接。

139. 发明授权

US08466473B2 Structure and method for Vt tuning and short channel control with high k/metal gate MOSFETs 有权
标题翻译：具有高k /金属栅极MOSFET的Vt调谐和短沟道控制的结构和方法
公开(公告)号：US08466473B2
公开(公告)日：2013-06-18
申请号：US12960589
申请日：2010-12-06
申请人： Jin Cai , Xiangdong Chen , Xinlin Wang
发明人： Jin Cai , Xiangdong Chen , Xinlin Wang
IPC分类号： H01L31/0312 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L21/8238
CPC分类号： H01L21/823892 , H01L21/823807 , H01L29/1041
摘要： A semiconductor device is provided that includes a semiconductor substrate having a well region located within an upper region thereof. A semiconductor material stack is located on the well region. The semiconductor material stack includes, from bottom to top, a semiconductor-containing buffer layer and a non-doped semiconductor-containing channel layer; the semiconductor-containing buffer layer of the semiconductor material stack is located directly on an upper surface of the well region. The structure also includes a gate material stack located directly on an upper surface of the non-doped semiconductor-containing channel layer. The gate material stack employed in the present disclosure includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a polysilicon layer.
摘要翻译：提供一种半导体器件，其包括具有位于其上部区域内的阱区的半导体衬底。半导体材料堆叠位于阱区上。半导体材料堆叠包括从底部到顶部的含半导体的缓冲层和非掺杂的含半导体的沟道层; 半导体材料堆叠的含半导体的缓冲层直接位于阱区的上表面。该结构还包括直接位于非掺杂半导体沟道层的上表面上的栅极材料堆叠。本公开中采用的栅极材料堆叠包括从底部到顶部的高k栅介质层，功函数金属层和多晶硅层。

140. 发明申请

US20130051112A1 FINFET Based One-Time Programmable Device and Related Method 有权
标题翻译：基于FINFET的一次性可编程器件及相关方法
公开(公告)号：US20130051112A1
公开(公告)日：2013-02-28
申请号：US13219414
申请日：2011-08-26
申请人： Wei Xia , Xiangdong Chen
发明人： Wei Xia , Xiangdong Chen
IPC分类号： G11C17/08
CPC分类号： H01L29/7855 , G11C11/34 , G11C17/12 , H01L23/5252 , H01L27/11206 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a one-time programmable (OTP) device comprises a memory FinFET in parallel with a sensing FinFET. The memory FinFET and the sensing FinFET share a common source region, a common drain region, and a common channel region. The memory FinFET is programmed by having a ruptured gate dielectric, resulting in the sensing FinFET having an altered threshold voltage and an altered drain current. A method for utilizing such an OTP device comprises applying a programming voltage for rupturing the gate dielectric of the memory FinFET thereby achieving a programmed state of the memory FinFET, and detecting by the sensing FinFET the altered threshold voltage and the altered drain current due to the programmed state of the memory FinFET.
摘要翻译：根据一个实施例，一次性可编程（OTP）器件包括与感测FinFET并联的存储器FinFET。存储器FinFET和感测FinFET共享共源极区，公共漏极区和公共沟道区。存储器FinFET通过具有破裂的栅极电介质来编程，导致感测FinFET具有改变的阈值电压和改变的漏极电流。一种利用这种OTP器件的方法包括施加用于破坏存储器FinFET的栅极电介质的编程电压，从而实现存储器FinFET的编程状态，并且通过感测FinFET检测改变的阈值电压和改变的漏极电流，由于存储器FinFET的编程状态。

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