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131. 发明授权

US06429128B1 Method of forming nitride capped Cu lines with reduced electromigration along the Cu/nitride interface 有权
标题翻译：沿Cu /氮化物界面形成具有减少的电迁移的氮化物封盖的Cu线的方法
公开(公告)号：US06429128B1
公开(公告)日：2002-08-06
申请号：US09902587
申请日：2001-07-12
申请人： Paul Raymond Besser , Minh Van Ngo , Larry Zhao
发明人： Paul Raymond Besser , Minh Van Ngo , Larry Zhao
IPC分类号： H01L2144
CPC分类号： H01L21/76862 , H01L21/3185 , H01L21/76834 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The electromigration resistance of nitride capped Cu lines is significantly improved by controlling the nitride deposition conditions to reduce the compressive stress of the deposited nitride layer, thereby reducing diffusion along the Cu-nitride interface. Embodiments include depositing a silicon nitride capping layer on inlaid Cu at a reduced RF power, e.g., about 400 to about 500 watts and an increased spacing, e.g., about 680 to about 720 mils, to reduce the compressive stress of the deposited silicon nitride layer to below about 2×107 Pascals. Embodiments also include sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a soft plasma containing NH3 diluted with N2, ramping up the introduction of SiH4 and then initiating plasma enhanced chemical vapor deposition of a silicon nitride capping layer, while maintaining substantially the same pressure and N2 flow rate during plasma treatment, SiH4 ramp up and silicon nitride deposition. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.
摘要翻译：通过控制氮化物沉积条件以减小沉积的氮化物层的压应力，从而减少沿着Cu-氮化物界面的扩散，显着改善了氮化物覆盖的Cu线的电迁移电阻。实施例包括以降低的RF功率（例如，约400至约500瓦特）和增加的间隔（例如，约680至约720密耳）在镶嵌的Cu上沉积氮化硅覆盖层，以减小沉积的氮化硅层的压应力低于约2×107帕斯卡。实施例还包括用包含用N 2稀释的NH 3的软质等离子体连续和连续地处理嵌入的Cu的暴露的平坦化表面，使引入SiH4升高，然后启动氮化硅覆盖层的等离子体增强化学气相沉积，同时保持基本上在等离子体处理期间，相同的压力和N2的流速，SiH4斜坡上升和氮化硅沉积。实施例还包括形成在介电常数（k）小于约3.9的电介质材料中的Cu双镶嵌结构。

132. 发明授权

US06403474B1 Controlled anneal conductors for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的受控退火导体
公开(公告)号：US06403474B1
公开(公告)日：2002-06-11
申请号：US09745917
申请日：2000-12-20
申请人： Steven C. Avanzino , Pin-Chin Connie Wang , Minh Van Ngo
发明人： Steven C. Avanzino , Pin-Chin Connie Wang , Minh Van Ngo
IPC分类号： H01L2144
CPC分类号： H01L21/76877 , H01L21/2885 , H01L21/76883
摘要： A method is provided for manufacturing an integrated circuit on a semiconductor wafer having a semiconductor substrate with a semiconductor device thereon. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening. A seed layer is deposited on the barrier layer and securely bonds to the barrier layer. A conductor layer is deposited to fill the channel opening over the barrier layer. A planarization technique is used to planarize the barrier, seed layer, and conductor layers to be coplanar with the dielectric layer to form a conductor channel. The semiconductor wafer is then subjected to a two step timed anneal.
摘要翻译：提供了一种用于在其上具有半导体器件的半导体衬底的半导体晶片上制造集成电路的方法。在半导体衬底上形成电介质层，并在电介质层中形成开口。沉积阻挡层以使开口线对齐。种子层沉积在阻挡层上并牢固地结合到阻挡层上。沉积导体层以填充阻挡层上的通道开口。平面化技术用于平坦化屏障，晶种层和与电介质层共面的导体层，以形成导体沟道。然后对半导体晶片进行两步定时退火。

133. 发明授权

US06383925B1 Method of improving adhesion of capping layers to cooper interconnects 有权
标题翻译：提高封盖层对铜互连的粘附性的方法
公开(公告)号：US06383925B1
公开(公告)日：2002-05-07
申请号：US09497850
申请日：2000-02-04
申请人： Minh Van Ngo , Lu You , Robert A. Huertas , Ercan Adem
发明人： Minh Van Ngo , Lu You , Robert A. Huertas , Ercan Adem
IPC分类号： H01L2144
CPC分类号： H01L21/76838 , H01L21/76834 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The adhesion of a barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member, after CMP, in a reaction chamber with a plasma containing ammonia and nitrogen for a brief period of time to reduce the surface oxide and then introducing silane into the reaction chamber to deposit the barrier layer, e.g., silicon nitride, under high density plasma conditions in the presence of nitrogen. The presence of nitrogen during plasma oxide layer reduction and plasma barrier layer deposition significantly improves adhesion of the barrier layer to the Cu or Cu alloy surface.
摘要翻译：通过在具有氨和氮气的等离子体的反应室中处理Cu或Cu合金互连构件的CMP暴露表面之后，通过将Cu或Cu合金互连构件的阻挡层或覆盖层的粘合性显着提高，一段时间以减少表面氧化物，然后将硅烷引入反应室，以在氮气存在下在高密度等离子体条件下沉积阻挡层，例如氮化硅。在等离子体氧化物层还原和等离子体阻挡层沉积期间氮的存在显着提高了阻挡层对Cu或Cu合金表面的粘附性。

134. 发明授权

US06380588B1 Semiconductor device having uniform spacers 有权
标题翻译：具有均匀间隔物的半导体器件
公开(公告)号：US06380588B1
公开(公告)日：2002-04-30
申请号：US09567013
申请日：2000-05-09
申请人： William G. En , Minh Van Ngo , Chih-Yuk Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
发明人： William G. En , Minh Van Ngo , Chih-Yuk Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
IPC分类号： H01L2100
CPC分类号： H01L21/31116
摘要： A semiconductor device having both functional and non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.
摘要翻译：具有功能和非功能或虚拟线，区域和/或图案的半导体器件，以产生导致随后形成的间隔物在形状和尺寸上更可预测和均匀的拓扑。

135. 发明授权

US06376389B1 Method for eliminating anti-reflective coating in semiconductors 有权
标题翻译：消除半导体抗反射涂层的方法
公开(公告)号：US06376389B1
公开(公告)日：2002-04-23
申请号：US09588117
申请日：2000-05-31
申请人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
发明人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
IPC分类号： H01L2100
CPC分类号： H01L21/76802 , H01L21/76895 , H01L23/522 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor device without the use of an anti-reflective coating. In one embodiment, electrical devices are formed on a semiconductor substrate. A material with a low dielectric constant such as an oxide is then deposited. The low dielectric layer is then covered with photoresist and photolithographically processed and subsequently developed. The low dielectric layer is then etched using the pattern formed on the photoresist and the photoresist is later removed. Because this process works in any similar circumstances, good examples of its application are the formation of both contacts and local interconnects.
摘要翻译：本发明提供一种不使用抗反射涂层的半导体器件的制造方法。在一个实施例中，电子器件形成在半导体衬底上。然后沉积具有低介电常数的材料，例如氧化物。然后用光致抗蚀剂覆盖低介电层，并进行光刻处理并随后显影。然后使用形成在光致抗蚀剂上的图案蚀刻低介电层，随后去除光致抗蚀剂。因为这个过程在任何类似的情况下都可以工作，它的应用的很好的例子是形成两个触点和局部互连。

136. 发明授权

US06297148B1 Method of forming a silicon bottom anti-reflective coating with reduced junction leakage during salicidation 有权
标题翻译：形成硅底部抗反射涂层的方法，其在硫化过程中具有减少的结渗漏
公开(公告)号：US06297148B1
公开(公告)日：2001-10-02
申请号：US09477808
申请日：2000-01-05
申请人： Paul Besser , Minh Van Ngo , Yowjuang Bill Liu
发明人： Paul Besser , Minh Van Ngo , Yowjuang Bill Liu
IPC分类号： H01L214763
CPC分类号： H01L21/28518
摘要： A method of performing ultra-shallow junctions in a semiconductor wafer uses a silicon layer to achieve ultra-low silicon consumption during a salicide formation process. A refractory metal layer, such as a cobalt layer, is deposited over the gate and source/drain junctions of the semiconductor device. After a rapid thermal annealing is performed to form the high-ohmic phase of the salicide, a silicon layer is deposited at a low temperature over the semiconductor device. The silicon layer provides a source of silicon for consumption during a second thermal annealing step, reducing the amount of silicon of the source/drain junctions that is consumed. The second thermal annealing step is performed in a nitrogen and oxygen atmosphere so at the silicon layer is transformed into a silicon oxynitride bottom anti-reflective coating layer.
摘要翻译：在半导体晶片中进行超浅结的方法使用硅层，以在自对准硅化物形成工艺期间实现超低硅消耗。诸如钴层的难熔金属层沉积在半导体器件的栅极和源极/漏极结上。在进行快速热退火以形成硅化物的高欧姆相后，在低温下在半导体器件上沉积硅层。硅层在第二热退火步骤期间提供用于消耗的硅源，减少消耗的源极/漏极结的硅的量。第二热退火步骤在氮和氧气氛中进行，因此在硅层转变为氮氧化硅底部抗反射涂层。

137. 发明授权

US06251776B1 Plasma treatment to reduce stress corrosion induced voiding of patterned metal layers 有权
标题翻译：等离子体处理以减少应力腐蚀导致图案化金属层的排空
公开(公告)号：US06251776B1
公开(公告)日：2001-06-26
申请号：US09283754
申请日：1999-04-02
申请人： Minh Van Ngo , Simon S. Chan , Anne E. Sanderfer , King Wai Kelwin Ko
发明人： Minh Van Ngo , Simon S. Chan , Anne E. Sanderfer , King Wai Kelwin Ko
IPC分类号： H01L21441
CPC分类号： H01L21/02071 , H01L21/02052 , H01L21/02054 , H01L21/76838
摘要： Stress corrosion induced voiding of patterned metal layers is avoided or substantially reduced by removing etching residues before gap filling. Embodiments include etching an Al or Al alloy layer employing fluorine and/or chlorine chemistry, wet cleaning, treating with a plasma containing ammonia or ammonia and oxygen at a temperature of at least about 400° C. and gap filling with a dielectric material, e.g. HDP oxide by HDP CVD.
摘要翻译：通过在间隙填充之前去除蚀刻残留物来避免或显着减少图形化金属层的应力腐蚀引起的空隙。实施例包括使用氟和/或氯化学，湿洗，用至少约400℃的温度下含有氨或氨和等离子体的等离子体进行蚀刻Al或Al合金层，以及填充介电材料的间隙。 HDP CVD的HDP氧化物。

138. 发明授权

US06236091B1 Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide 有权
标题翻译：形成具有改善的二氧化硅/硅化物蚀刻选择性的局部互连的方法
公开(公告)号：US06236091B1
公开(公告)日：2001-05-22
申请号：US09408845
申请日：1999-09-30
申请人： Minh Van Ngo , Angela Hui
发明人： Minh Van Ngo , Angela Hui
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L21/76895 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method and arrangement for forming a local interconnect without weakening the field edge or disconnecting the diffusion region at the field edge provides an etch stop layer with increased hardness in comparison to conventional etch stop layers, such as plasma enhanced chemical vapor deposition (PECVD) SiON etch stop layers. A PECVD process is used to deposit silicon carbide (SiC). The increased hardness of the SiC etch stop layer is slower to etch than conventional PECVD SiON so that when etching the dielectric layer in which the local interconnect material is subsequently deposited, the etching stops at the etch stop layer in a controlled manner. This prevents the unintentional etching of the silicide region and diffusion region at the field edge.
摘要翻译：与常规蚀刻停止层（例如等离子体增强化学气相沉积（PECVD）SiON）相比，用于在不削弱场边缘或在场边缘处断开扩散区域的情况下形成局部互连的方法和装置提供了具有增加的硬度的蚀刻停止层蚀刻停止层。使用PECVD工艺沉积碳化硅（SiC）。 SiC蚀刻停止层的硬度增加比常规PECVD SiON蚀刻更慢，使得当蚀刻其中随后沉积局部互连材料的介电层时，蚀刻以受控的方式在蚀刻停止层处停止。这防止了在场边缘处的硅化物区域和扩散区域的无意蚀刻。

139. 发明授权

US06225210B1 High density capping layers with improved adhesion to copper interconnects 有权
标题翻译：高密度封盖层，具有改善与铜互连的粘附性
公开(公告)号：US06225210B1
公开(公告)日：2001-05-01
申请号：US09207675
申请日：1998-12-09
申请人： Minh Van Ngo , Robin W. Cheung
发明人： Minh Van Ngo , Robin W. Cheung
IPC分类号： H01L214763
CPC分类号： H01L21/3185 , H01L21/76834 , H01L21/76877
摘要： The adhesion of a barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by depositing the capping layer under high density plasma conditions at an elevated temperature, such as about 450° C. to about 650° C., e.g. about 450° C. to about 550° C. High density plasma deposition at such elevated temperatures increases the surface roughness of the exposed Cu metallization, thereby increasing adhesion of the deposited capping layer, such as silicon nitride and increasing the density of the silicon nitride capping layer thereby improving its etch stop characteristics. Embodiments of the present invention include treating the exposed surface of the Cu or Cu alloy interconnect member after CMP in a hydrogen-containing plasma, and depositing a silicon nitride capping layer under high density plasma conditions on the treated surface.
摘要翻译：通过在高温等离子体条件下，例如约450℃至约650℃，例如高温等离子体条件下沉积封盖层，显着增强了阻挡层或覆盖层对Cu或Cu合金互连构件的粘附。约450℃至约550℃。在这种升高的温度下的高密度等离子体沉积增加了暴露的Cu金属化的表面粗糙度，从而增加沉积的覆盖层（例如氮化硅）的粘附并增加氮化硅的密度从而改善其蚀刻停止特性。本发明的实施例包括在含氢等离子体中处理CMP之后的Cu或Cu合金互连构件的暴露表面，并在经处理的表面上在高密度等离子体条件下沉积氮化硅覆盖层。

140. 发明授权

US06221793B1 Process for forming PECVD undoped oxide with a super low deposition rate on a single state deposition 有权
标题翻译：在单一状态沉积下以超低沉积速率形成PECVD未掺杂氧化物的方法
公开(公告)号：US06221793B1
公开(公告)日：2001-04-24
申请号：US09517092
申请日：2000-03-01
申请人： Minh Van Ngo , Hartmut Ruelke , Robert A. Huertas
发明人： Minh Van Ngo , Hartmut Ruelke , Robert A. Huertas
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , C23C16/402 , H01L21/02211 , H01L21/02274 , H01L21/31612
摘要： A process for super low deposition rate plasma enhanced chemical vapor deposition (PECVD) of undoped oxide on a single station deposition is provided. A very thin PECVD oxide layer used, for instance, as an oxide liner between a polysilicon gate and a nitride spacer, may be produced in a PECVD chamber with a reduced flow rate of silane, nitrous oxide and molecular nitrogen. The deposition rate may be lowered to 20 angstroms/minute, for example, with this long deposition time providing a better process control. At the same time, the film is dense, silicon rich, highly compressive, provides excellent step coverage and acceptable thickness uniformity.
摘要翻译：提供了一种用于单站沉积的超低沉积速率等离子体增强化学气相沉积（PECVD）未掺杂氧化物的方法。例如，可以在具有降低的硅烷，一氧化二氮和分子氮的流速的PECVD室中产生非常薄的PECVD氧化物层，例如，作为多晶硅栅极和氮化物间隔物之间的氧化物衬垫。沉积速率可以降低到20埃/分钟，例如，这种长的沉积时间提供更好的工艺控制。同时，薄膜致密，富硅，高压缩，提供优异的台阶覆盖和可接受的厚度均匀性。

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