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131. 发明申请

US20080224231A1 TRANSISTORS HAVING V-SHAPE SOURCE/DRAIN METAL CONTACTS 审中-公开
标题翻译：具有V形形状/漏极金属接触的晶体管
公开(公告)号：US20080224231A1
公开(公告)日：2008-09-18
申请号：US12105298
申请日：2008-04-18
申请人： Huilong Zhu , Haining Yang , Zhijiong Luo
发明人： Huilong Zhu , Haining Yang , Zhijiong Luo
IPC分类号： H01L29/76
CPC分类号： H01L29/7834 , H01L21/76816 , H01L21/84 , H01L23/485 , H01L29/41733 , H01L29/41766 , H01L29/665 , H01L29/66636
摘要： A semiconductor structure. The semiconductor structure includes (a) a semiconductor layer, (b) a gate dielectric region, and (c) a gate electrode region. The gate electrode region is electrically insulated from the semiconductor layer. The semiconductor layer comprises a channel region, a first and a second source/drain regions. The channel region is disposed between the first and second source/drain regions and directly beneath and electrically insulated from the gate electrode region. The semiconductor structure further includes (d) a first and a second electrically conducting regions, and (e) a first and a second contact regions. The first electrically conducting region and the first source/drain region are in direct physical contact with each other at a first and a second common surfaces. The first and second common surfaces are not coplanar. The first contact region overlaps both the first and second common surfaces.
摘要翻译：半导体结构。半导体结构包括（a）半导体层，（b）栅极电介质区域和（c）栅电极区域。栅电极区域与半导体层电绝缘。半导体层包括沟道区，第一和第二源极/漏极区。沟道区域设置在第一和第二源极/漏极区域之间，并且直接位于栅电极区域下方并与栅电极区域电绝缘。半导体结构还包括（d）第一和第二导电区域，以及（e）第一和第二接触区域。第一导电区域和第一源极/漏极区域在第一和第二共同表面处彼此直接物理接触。第一和第二公共表面不共面。第一接触区域与第一和第二公共表面重叠。

132. 发明申请

US20080185645A1 SEMICONDUCTOR STRUCTURE INCLUDING STEPPED SOURCE/DRAIN REGION 审中-公开
标题翻译：半导体结构，包括步进源/排水区
公开(公告)号：US20080185645A1
公开(公告)日：2008-08-07
申请号：US11670100
申请日：2007-02-01
申请人： Zhijiong Luo , Huilong Zhu , Sunfei Fang , Thomas W. Dyer
发明人： Zhijiong Luo , Huilong Zhu , Sunfei Fang , Thomas W. Dyer
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/28518 , H01L23/485 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/7834 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a stepped source and drain region located in part within a semiconductor substrate that preferably has a step in a direction of a gate electrode located over a channel region that adjoins the stepped source and drain region within the semiconductor substrate. A stepped portion of the stepped source and drain region covers an extension region within the stepped source and drain region.
摘要翻译：半导体结构包括部分地位于半导体衬底内的阶梯式源极和漏极区域，其优选地具有位于与半导体衬底内的阶梯式源极和漏极区域相邻的沟道区域上的栅极电极的方向上的台阶。阶梯式源极和漏极区域的阶梯部分覆盖阶梯式源极和漏极区域内的延伸区域。

133. 发明申请

US20080006818A1 STRUCTURE AND METHOD TO FORM MULTILAYER EMBEDDED STRESSORS 有权
标题翻译：形成多层嵌入式应力的结构和方法
公开(公告)号：US20080006818A1
公开(公告)日：2008-01-10
申请号：US11423227
申请日：2006-06-09
申请人： Zhijiong Luo , Ricky S. Amos , Nivo Rovedo , Henry K. Utomo
发明人： Zhijiong Luo , Ricky S. Amos , Nivo Rovedo , Henry K. Utomo
IPC分类号： H01L31/00 , H01L29/06
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L29/1083 , H01L29/165 , H01L29/6656 , H01L29/66636
摘要： A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.
摘要翻译：提供了具有用于在器件沟道区域上诱发应变的半导体结构中的渐变掺杂物分布的多层嵌入式应力器。本发明的多层应力器形成在源极/漏极区域通常位于其中的半导体结构的区域内。本发明的多层应力器包括未掺杂或轻掺杂的第一共形外延半导体层和相对于第一外延半导体层高度掺杂的第二外延半导体层。第一和第二外延半导体层各自具有相同的晶格常数，其不同于嵌入其中的衬底。包括本发明的多层嵌入式应力器的结构在应力接近和短沟道效应之间实现良好的平衡，甚至消除或基本上减少在深源/漏区形成期间通常产生的任何可能的缺陷。

134. 发明授权

US07309901B2 Field effect transistors (FETs) with multiple and/or staircase silicide 失效
标题翻译：具有多个和/或阶梯硅化物的场效应晶体管（FET）
公开(公告)号：US07309901B2
公开(公告)日：2007-12-18
申请号：US10908087
申请日：2005-04-27
申请人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
发明人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
IPC分类号： H01L21/8232
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6659
摘要： A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical contact with first and second S/D regions, respective. First and second silicide regions are formed such that the first silicide region is in direct physical contact with the first S/D region and the first S/D extension region, whereas the second silicide region is in direct physical contact with the second S/D region and the second S/D extension region. The first silicide region is thinner for regions in contact with first S/D extension region than for regions in contact with the first S/D region. Similarly, the second silicide region is thinner for regions in contact with second S/D extension region than for regions in contact with the second S/D region.
摘要翻译：一种半导体结构及其形成方法。半导体结构包括场效应晶体管（FET），其具有设置在第一和第二源极/漏极（S / D）延伸区域之间的沟道区域，第一和第二源极/漏极（S / D）延伸区域又分别与第一和第二S / D区域直接物理接触。形成第一和第二硅化物区域，使得第一硅化物区域与第一S / D区域和第一S / D延伸区域直接物理接触，而第二硅化物区域与第二S / D区域直接物理接触区域和第二S / D扩展区域。对于与第一S / D延伸区域接触的区域，第一硅化物区域比与第一S / D区域接触的区域更薄。类似地，对于与第二S / D延伸区域接触的区域，第二硅化物区域比与第二S / D区域接触的区域更薄。

135. 发明申请

US20070269952A1 METHOD OF FABRICATING A TRANSISTOR STRUCTURE 有权
标题翻译：制造晶体管结构的方法
公开(公告)号：US20070269952A1
公开(公告)日：2007-11-22
申请号：US11383952
申请日：2006-05-17
申请人： Yung Fu Chong , Kevin K. Dezfulian , Zhijiong Luo , Huilong Zhu
发明人： Yung Fu Chong , Kevin K. Dezfulian , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/3065 , H01L21/31116 , H01L29/165 , H01L29/6653 , H01L29/6659 , H01L29/66628 , H01L29/66636
摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. There is provided a method of forming a strained channel transistor structure on a substrate, comprising the steps of: forming a source stressor recess comprising a deep source recess and a source extension recess; forming a drain stressor recess comprising a deep drain recess and a drain extension recess; and subsequently forming a source stressor in said source stressor recess and a drain stressor in said drain stressor recess. The deep source/drain and source/drain extension stressors are formed by an uninterrupted etch process and an uninterrupted epitaxy process.
摘要翻译：本发明涉及半导体集成电路。更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。提供了一种在衬底上形成应变通道晶体管结构的方法，包括以下步骤：形成包括深源凹槽和源极延伸凹槽的源极应力器凹部; 形成包括深排水凹槽和排水延伸凹槽的排水应力槽; 并且随后在所述源应力器凹部中形成源应力器，以及在所述漏应力器凹部中形成漏应力器。深源/漏极和源极/漏极延伸应力源通过不间断的蚀刻工艺和不间断的外延工艺形成。

136. 发明申请

US20070249131A1 Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors 有权
标题翻译：用于形成金属栅极和全硅化栅场效应晶体管的光热退火方法
公开(公告)号：US20070249131A1
公开(公告)日：2007-10-25
申请号：US11408522
申请日：2006-04-21
申请人： Scott Allen , Cyril Cabral , Kevin Dezfulian , Sunfei Fang , Brian Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement Wann , Huilong Zhu
发明人： Scott Allen , Cyril Cabral , Kevin Dezfulian , Sunfei Fang , Brian Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement Wann , Huilong Zhu
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译：用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害金属门。另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

137. 发明申请

US20070122955A1 METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE 失效
标题翻译：制造半导体结构的方法
公开(公告)号：US20070122955A1
公开(公告)日：2007-05-31
申请号：US11164568
申请日：2005-11-29
申请人： Zhijiong Luo , Yung Chong , Huilong Zhu
发明人： Zhijiong Luo , Yung Chong , Huilong Zhu
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L21/823864 , H01L29/4975 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/7848
摘要： There is provided a method of manufacturing a field effect transistor (FET) that includes the steps of forming a gate structure on a semiconductor substrate, and forming a recess in the substrate and embedding a second semiconductor material in the recess. The gate structure includes a gate dielectric layer, conductive layers and an insulating layer. Forming said gate structure includes a step of recessing the conductive layer in the gate structure, and the steps of recessing the conductive layer and forming the recess in the substrate are performed in a single step. There is also provided a FET device.
摘要翻译：提供了一种制造场效应晶体管（FET）的方法，该方法包括以下步骤：在半导体衬底上形成栅极结构，并在衬底中形成凹陷并将第二半导体材料嵌入凹槽中。栅极结构包括栅极电介质层，导电层和绝缘层。形成所述栅极结构包括使栅极结构中的导电层凹陷的步骤，并且在单个步骤中执行使导电层凹陷并且在衬底中形成凹部的步骤。还提供了一种FET器件。

138. 发明申请

US20070105299A1 DUAL STRESS MEMORY TECHNIQUE METHOD AND RELATED STRUCTURE 有权
标题翻译：双应力记忆技术方法及相关结构
公开(公告)号：US20070105299A1
公开(公告)日：2007-05-10
申请号：US11164114
申请日：2005-11-10
申请人： Sunfei Fang , Jun Kim , Zhijiong Luo , Hung Ng , Nivo Rovedo , Young Teh
发明人： Sunfei Fang , Jun Kim , Zhijiong Luo , Hung Ng , Nivo Rovedo , Young Teh
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864 , H01L21/823807
摘要： A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.
摘要翻译：公开了一种在包括nFET和PFET以及相关结构的半导体器件中提供双重应力记忆技术的方法。该方法的一个实施例包括在nFET上形成拉伸应力层，并在pFET上形成压应力层，退火以在半导体器件中记忆应力并去除应力层。压应力层可以包括使用高密度等离子体（HDP）沉积方法沉积的高应力氮化硅。退火步骤可以包括使用约400-1200℃的温度。高应力压缩氮化硅和/或退火温度确保压应力记忆保留在pFET中。

139. 发明授权

US07105440B2 Self-forming metal silicide gate for CMOS devices 失效
标题翻译：用于CMOS器件的自成型金属硅化物栅极
公开(公告)号：US07105440B2
公开(公告)日：2006-09-12
申请号：US10905629
申请日：2005-01-13
申请人： Zhijiong Luo , Sunfei Fang , Huilong Zhu
发明人： Zhijiong Luo , Sunfei Fang , Huilong Zhu
IPC分类号： H01L21/44
CPC分类号： H01L29/4975 , H01L21/28097 , H01L21/823835 , H01L29/665 , H01L29/7833
摘要： A process for forming a metal suicide gate in an FET device, where the suicide is self-forming (that is, formed without the need for a separate metal/silicon reaction step), and no CMP or etchback of the silicon material is required. A first layer of silicon material (polysilicon or amorphous silicon) is formed overlying the gate dielectric; a layer of metal is then formed on the first layer, and a second layer of silicon on the metal layer. A high-temperature (>700° C.) processing step, such as source/drain activation anneal, is subsequently performed; this step is effective to form a silicide layer above the gate dielectric by reaction of the metal with silicon in the first layer. A second high-temperature processing step (such as source/drain silicidation) may be performed which is effective to form a second silicide layer from silicon in the second layer. The thicknesses of the layers are such that in the high-temperature processing, substantially all of the first layer and at least a portion of the second layer are replaced by silicide material. Accordingly, a fully silicided gate structure may be produced.
摘要翻译：在FET器件中形成金属硅化物栅极的方法，其中硅化物自成型（即，不需要单独的金属/硅反应步骤形成），并且不需要CMP材料的CMP或回蚀。第一层硅材料（多晶硅或非晶硅）形成在栅极电介质上方; 然后在第一层上形成金属层，在金属层上形成第二层硅。随后进行高温（> 700℃）处理步骤，例如源极/漏极激活退火; 该步骤通过金属与第一层中的硅的反应在栅电介质上形成硅化物层是有效的。可以进行第二高温处理步骤（例如源极/漏极硅化），其有效地从第二层中的硅形成第二硅化物层。层的厚度使得在高温处理中，基本上所有的第一层和第二层的至少一部分被硅化物材料代替。因此，可以产生完全硅化的栅极结构。

140. 发明申请

US20060163569A1 Test structure of semiconductor device 有权
标题翻译：半导体器件的测试结构
公开(公告)号：US20060163569A1
公开(公告)日：2006-07-27
申请号：US11218397
申请日：2005-09-02
申请人： Min-chul Sun , Ja-hum Ku , Brian Greene , Manfred Eller , Wee Tan , Sunfei Fang , Zhijiong Luo
发明人： Min-chul Sun , Ja-hum Ku , Brian Greene , Manfred Eller , Wee Tan , Sunfei Fang , Zhijiong Luo
IPC分类号： H01L23/58 , H01L29/10
CPC分类号： H01L22/34
摘要： A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.
摘要翻译：提供半导体器件的测试结构。测试结构包括半导体衬底，晶体管，其包括形成在限定在半导体衬底内的第一和第二有源区上的栅极电极以及布置在栅电极的两个侧壁处以位于第一和第二有源区内的第一和第二接合区域，第二有源区，并且是硅化的，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到硅化的第一和第二结区，并被检测并形成在与栅电极或半导体衬底相同的高度上。

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